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![Ley Foon Tan](/assets/img/avatar_default.png)
This fix issue when access config from PCIe switch. The PCIe controller need to send Type 0 config TLP if the targeting bus matches with the secondary bus number, which is when the TLP is targeting the immediate device on the link. The PCIe controller send Type 1 config TLP if the targeting bus is larger than the secondary bus, which is when the TLP is targeting the device not immediate on the link. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
435 lines
11 KiB
C
435 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel FPGA PCIe host controller driver
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*
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* Copyright (C) 2013-2018 Intel Corporation. All rights reserved
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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#define RP_TX_REG0 0x2000
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#define RP_TX_CNTRL 0x2004
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#define RP_TX_SOP BIT(0)
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#define RP_TX_EOP BIT(1)
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#define RP_RXCPL_STATUS 0x200C
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#define RP_RXCPL_SOP BIT(0)
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#define RP_RXCPL_EOP BIT(1)
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#define RP_RXCPL_REG 0x2008
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#define P2A_INT_STATUS 0x3060
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#define P2A_INT_STS_ALL 0xf
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#define P2A_INT_ENABLE 0x3070
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#define RP_CAP_OFFSET 0x70
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/* TLP configuration type 0 and 1 */
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#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
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#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
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#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
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#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
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#define TLP_PAYLOAD_SIZE 0x01
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#define TLP_READ_TAG 0x1d
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#define TLP_WRITE_TAG 0x10
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#define RP_DEVFN 0
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#define RP_CFG_ADDR(pcie, reg) \
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((pcie->hip_base) + (reg) + (1 << 20))
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#define RP_SECONDARY(pcie) \
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readb(RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
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#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
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#define TLP_CFGRD_DW0(pcie, bus) \
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((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGRD1 \
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: TLP_FMTTYPE_CFGRD0) << 24) | \
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TLP_PAYLOAD_SIZE)
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#define TLP_CFGWR_DW0(pcie, bus) \
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((((bus > RP_SECONDARY(pcie)) ? TLP_FMTTYPE_CFGWR1 \
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: TLP_FMTTYPE_CFGWR0) << 24) | \
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TLP_PAYLOAD_SIZE)
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#define TLP_CFG_DW1(pcie, tag, be) \
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(((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
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#define TLP_CFG_DW2(bus, dev, fn, offset) \
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(((bus) << 24) | ((dev) << 19) | ((fn) << 16) | (offset))
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#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
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#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
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#define TLP_HDR_SIZE 3
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#define TLP_LOOP 20000
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#define DWORD_MASK 3
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#define IS_ROOT_PORT(pcie, bdf) \
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((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
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/**
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* struct intel_fpga_pcie - Intel FPGA PCIe controller state
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* @bus: Pointer to the PCI bus
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* @cra_base: The base address of CRA register space
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* @hip_base: The base address of Rootport configuration space
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* @first_busno: This driver supports multiple PCIe controllers.
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* first_busno stores the bus number of the PCIe root-port
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* number which may vary depending on the PCIe setup.
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*/
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struct intel_fpga_pcie {
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struct udevice *bus;
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void __iomem *cra_base;
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void __iomem *hip_base;
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int first_busno;
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};
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/**
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* Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
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* translation from PCI bus to native BUS. Entire DDR region is mapped
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* into PCIe space using these registers, so it can be reached by DMA from
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* EP devices.
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* The BAR0 of bridge should be hidden during enumeration to avoid the
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* sizing and resource allocation by PCIe core.
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*/
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static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie,
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pci_dev_t bdf, int offset)
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{
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if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 &&
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PCI_FUNC(bdf) == 0 && offset == PCI_BASE_ADDRESS_0)
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return true;
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return false;
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}
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static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value,
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const u32 reg)
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{
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writel(value, pcie->cra_base + reg);
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}
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static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg)
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{
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return readl(pcie->cra_base + reg);
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}
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static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie)
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{
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return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA))
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& PCI_EXP_LNKSTA_DLLLA);
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}
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static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie,
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pci_dev_t bdf)
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{
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/* If there is no link, then there is no device */
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if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie))
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return false;
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/* access only one slot on each root port */
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if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0)
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return false;
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if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)
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return false;
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return true;
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}
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static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl)
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{
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cra_writel(pcie, reg0, RP_TX_REG0);
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cra_writel(pcie, ctrl, RP_TX_CNTRL);
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}
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static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value)
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{
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int i;
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u32 ctrl;
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u32 comp_status;
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u32 dw[4];
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u32 count = 0;
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for (i = 0; i < TLP_LOOP; i++) {
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ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
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if (!(ctrl & RP_RXCPL_SOP))
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continue;
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/* read first DW */
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dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
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/* Poll for EOP */
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for (i = 0; i < TLP_LOOP; i++) {
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ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
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dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
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if (ctrl & RP_RXCPL_EOP) {
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comp_status = TLP_COMP_STATUS(dw[1]);
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if (comp_status) {
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*value = pci_get_ff(PCI_SIZE_32);
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return 0;
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}
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if (value &&
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TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
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count >= 3)
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*value = dw[3];
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return 0;
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}
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}
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udelay(5);
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}
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dev_err(pcie->dev, "read TLP packet timed out\n");
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return -ENODEV;
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}
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static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers,
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u32 data)
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{
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tlp_write_tx(pcie, headers[0], RP_TX_SOP);
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tlp_write_tx(pcie, headers[1], 0);
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tlp_write_tx(pcie, headers[2], 0);
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tlp_write_tx(pcie, data, RP_TX_EOP);
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}
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static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
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int offset, u8 byte_en, u32 *value)
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{
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u32 headers[TLP_HDR_SIZE];
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u8 busno = PCI_BUS(bdf);
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headers[0] = TLP_CFGRD_DW0(pcie, busno);
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headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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tlp_write_packet(pcie, headers, 0);
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return tlp_read_packet(pcie, value);
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}
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static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf,
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int offset, u8 byte_en, u32 value)
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{
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u32 headers[TLP_HDR_SIZE];
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u8 busno = PCI_BUS(bdf);
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headers[0] = TLP_CFGWR_DW0(pcie, busno);
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headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en);
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headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset);
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tlp_write_packet(pcie, headers, value);
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return tlp_read_packet(pcie, NULL);
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}
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int intel_fpga_rp_conf_addr(struct udevice *bus, pci_dev_t bdf,
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uint offset, void **paddress)
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{
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struct intel_fpga_pcie *pcie = dev_get_priv(bus);
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*paddress = RP_CFG_ADDR(pcie, offset);
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return 0;
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}
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static int intel_fpga_pcie_rp_rd_conf(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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return pci_generic_mmap_read_config(bus, intel_fpga_rp_conf_addr,
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bdf, offset, valuep, size);
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}
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static int intel_fpga_pcie_rp_wr_conf(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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int ret;
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struct intel_fpga_pcie *pcie = dev_get_priv(bus);
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ret = pci_generic_mmap_write_config(bus, intel_fpga_rp_conf_addr,
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bdf, offset, value, size);
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if (!ret) {
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/* Monitor changes to PCI_PRIMARY_BUS register on root port
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* and update local copy of root bus number accordingly.
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*/
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if (offset == PCI_PRIMARY_BUS)
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pcie->first_busno = (u8)(value);
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}
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return ret;
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}
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static u8 pcie_get_byte_en(uint offset, enum pci_size_t size)
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{
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switch (size) {
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case PCI_SIZE_8:
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return 1 << (offset & 3);
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case PCI_SIZE_16:
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return 3 << (offset & 3);
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default:
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return 0xf;
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}
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}
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static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie,
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pci_dev_t bdf, uint offset,
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ulong *valuep, enum pci_size_t size)
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{
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int ret;
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u32 data;
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u8 byte_en;
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/* Uses memory mapped method to read rootport config registers */
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if (IS_ROOT_PORT(pcie, bdf))
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return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,
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offset, valuep, size);
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byte_en = pcie_get_byte_en(offset, size);
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ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK,
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byte_en, &data);
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if (ret)
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return ret;
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dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
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offset, size, data);
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*valuep = pci_conv_32_to_size(data, offset, size);
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return 0;
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}
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static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie,
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pci_dev_t bdf, uint offset,
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ulong value, enum pci_size_t size)
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{
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u32 data;
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u8 byte_en;
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dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
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offset, size, value);
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/* Uses memory mapped method to read rootport config registers */
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if (IS_ROOT_PORT(pcie, bdf))
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return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,
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value, size);
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byte_en = pcie_get_byte_en(offset, size);
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data = pci_conv_size_to_32(0, value, offset, size);
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return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK,
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byte_en, data);
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}
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static int pcie_intel_fpga_read_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct intel_fpga_pcie *pcie = dev_get_priv(bus);
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dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) {
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*valuep = (u32)pci_get_ff(size);
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return 0;
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}
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if (!intel_fpga_pcie_addr_valid(pcie, bdf)) {
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*valuep = (u32)pci_get_ff(size);
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return 0;
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}
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return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size);
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}
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static int pcie_intel_fpga_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct intel_fpga_pcie *pcie = dev_get_priv(bus);
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if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset))
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return 0;
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if (!intel_fpga_pcie_addr_valid(pcie, bdf))
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return 0;
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return _pcie_intel_fpga_write_config(pcie, bdf, offset, value,
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size);
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}
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static int pcie_intel_fpga_probe(struct udevice *dev)
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{
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struct intel_fpga_pcie *pcie = dev_get_priv(dev);
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pcie->bus = pci_get_controller(dev);
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pcie->first_busno = dev->seq;
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/* clear all interrupts */
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cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
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/* disable all interrupts */
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cra_writel(pcie, 0, P2A_INT_ENABLE);
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return 0;
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}
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static int pcie_intel_fpga_ofdata_to_platdata(struct udevice *dev)
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{
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struct intel_fpga_pcie *pcie = dev_get_priv(dev);
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struct fdt_resource reg_res;
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int node = dev_of_offset(dev);
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int ret;
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DECLARE_GLOBAL_DATA_PTR;
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ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
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"Cra", ®_res);
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if (ret) {
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dev_err(dev, "resource \"Cra\" not found\n");
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return ret;
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}
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pcie->cra_base = map_physmem(reg_res.start,
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fdt_resource_size(®_res),
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MAP_NOCACHE);
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ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",
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"Hip", ®_res);
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if (ret) {
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dev_err(dev, "resource \"Hip\" not found\n");
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return ret;
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}
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pcie->hip_base = map_physmem(reg_res.start,
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fdt_resource_size(®_res),
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MAP_NOCACHE);
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return 0;
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}
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static const struct dm_pci_ops pcie_intel_fpga_ops = {
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.read_config = pcie_intel_fpga_read_config,
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.write_config = pcie_intel_fpga_write_config,
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};
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static const struct udevice_id pcie_intel_fpga_ids[] = {
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{ .compatible = "altr,pcie-root-port-2.0" },
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{},
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};
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U_BOOT_DRIVER(pcie_intel_fpga) = {
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.name = "pcie_intel_fpga",
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.id = UCLASS_PCI,
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.of_match = pcie_intel_fpga_ids,
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.ops = &pcie_intel_fpga_ops,
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.ofdata_to_platdata = pcie_intel_fpga_ofdata_to_platdata,
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.probe = pcie_intel_fpga_probe,
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.priv_auto_alloc_size = sizeof(struct intel_fpga_pcie),
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};
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