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https://github.com/brain-hackers/u-boot-brain
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67a0652c47
iROM logic provides undesired jump address for CPU2. This patch adds a programmable susbstitute for a part of iROM logic which wakes up cores and provides jump addresses. This patch creates a logic to make all secondary cores jump to a particular address which evades the possibility of CPU2 jumping to wrong address and create undesired results. Logic of the workaround: Step-1: iROM code checks value at address 0x2020028. Step-2: If value is 0xc9cfcfcf, it jumps to the address (0x202000+CPUid*4), else, it continues executing normally. Step-3: Primary core puts secondary cores in WFE and store 0xc9cfcfcf in 0x2020028 and jump address (pointer to function low_power_start) in (0x202000+CPUid*4). Step-4: When secondary cores recieve event signal they jump to this address and continue execution. Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
19 lines
459 B
Makefile
19 lines
459 B
Makefile
#
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# Copyright (C) 2009 Samsung Electronics
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# Minkyu Kang <mk7.kang@samsung.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
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obj-$(CONFIG_EXYNOS5420) += sec_boot.o
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
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obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
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obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
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obj-y += spl_boot.o
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obj-y += lowlevel_init.o
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endif
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