mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 15:53:46 +09:00
5750e5e29a
Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
130 lines
2.8 KiB
C
130 lines
2.8 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUARK_H_
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#define _QUARK_H_
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/* Message Bus Ports */
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#define MSG_PORT_MEM_ARBITER 0x00
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#define MSG_PORT_HOST_BRIDGE 0x03
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#define MSG_PORT_RMU 0x04
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#define MSG_PORT_MEM_MGR 0x05
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#define MSG_PORT_SOC_UNIT 0x31
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/* Port 0x00: Memory Arbiter Message Port Registers */
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/* Enhanced Configuration Space */
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#define AEC_CTRL 0x00
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/* Port 0x03: Host Bridge Message Port Registers */
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/* Host Miscellaneous Controls 2 */
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#define HMISC2 0x03
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#define HMISC2_SEGE 0x00000002
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#define HMISC2_SEGF 0x00000004
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#define HMISC2_SEGAB 0x00000010
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/* Host Memory I/O Boundary */
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#define HM_BOUND 0x08
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/* Extended Configuration Space */
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#define HEC_REG 0x09
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/* Port 0x04: Remote Management Unit Message Port Registers */
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/* ACPI PBLK Base Address Register */
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#define PBLK_BA 0x70
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/* SPI DMA Base Address Register */
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#define SPI_DMA_BA 0x7a
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/* Port 0x05: Memory Manager Message Port Registers */
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/* eSRAM Block Page Control */
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#define ESRAM_BLK_CTRL 0x82
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#define ESRAM_BLOCK_MODE 0x10000000
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/* DRAM */
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#define DRAM_BASE 0x00000000
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#define DRAM_MAX_SIZE 0x80000000
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/* eSRAM */
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#define ESRAM_SIZE 0x80000
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/* Memory BAR Enable */
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#define MEM_BAR_EN 0x00000001
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/* I/O BAR Enable */
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#define IO_BAR_EN 0x80000000
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/* 64KiB of RMU binary in flash */
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#define RMU_BINARY_SIZE 0x10000
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/* Legacy Bridge PCI Configuration Registers */
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#define LB_GBA 0x44
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#define LB_PM1BLK 0x48
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#define LB_GPE0BLK 0x4c
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#define LB_ACTL 0x58
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#define LB_PABCDRC 0x60
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#define LB_PEFGHRC 0x64
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#define LB_WDTBA 0x84
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#define LB_BCE 0xd4
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#define LB_BC 0xd8
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#define LB_RCBA 0xf0
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#ifndef __ASSEMBLY__
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/* Root Complex Register Block */
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struct quark_rcba {
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u32 rctl;
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u32 esd;
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u32 rsvd1[3150];
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u16 rmu_ir;
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u16 d23_ir;
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u16 core_ir;
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u16 d20d21_ir;
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};
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#include <asm/io.h>
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#include <asm/pci.h>
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/**
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* qrk_pci_read_config_dword() - Read a configuration value
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*
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* @dev: PCI device address: bus, device and function
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* @offset: Dword offset within the device's configuration space
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* @valuep: Place to put the returned value
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*
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* Note: This routine is inlined to provide better performance on Quark
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*/
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static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
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u32 *valuep)
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{
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outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
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*valuep = inl(PCI_REG_DATA);
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}
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/**
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* qrk_pci_write_config_dword() - Write a PCI configuration value
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*
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* @dev: PCI device address: bus, device and function
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* @offset: Dword offset within the device's configuration space
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* @value: Value to write
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*
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* Note: This routine is inlined to provide better performance on Quark
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*/
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static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
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u32 value)
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{
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outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
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outl(value, PCI_REG_DATA);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _QUARK_H_ */
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