York Sun 57495e4e5e powerpc/mpc8xxx: Update DDR registers ... DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be set for speed lower than 1250MT/s. CDR1 and CDR2 are control driver registers. ODT termination valueis for IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is 000 -> Termsel off 001 -> 120 Ohm 010 -> 180 Ohm 011 -> 75 Ohm 100 -> 110 Ohm 101 -> 60 Ohm 110 -> 70 Ohm 111 -> 47 Ohm Add two write leveling registers. Each QDS now has its own write leveling start value. In case of zero value, the value of QDS0 will be used. These values are board-specific and are set in board files. Extend DDR register timing_cfg_1 to have 4 bits for each field. DDR control driver registers and write leveling registers are added to interactive debugging for easy access. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-10-22 14:31:26 -05:00
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74xx_7xx	unify version_string	2011-07-28 17:22:53 +02:00
mpc5xx	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
mpc5xxx	usb: lowlevel interface change to support multiple controllers	2012-10-15 11:54:00 -07:00
mpc8xx	serial: mpc8xx: Move serial registration from serial_initialize()	2012-10-15 11:53:49 -07:00
mpc8xxx	powerpc/mpc8xxx: Update DDR registers	2012-10-22 14:31:26 -05:00
mpc83xx	MPC83xx, MPC85xx: compile stub cache function	2012-07-21 23:37:48 +02:00
mpc85xx	powerpc/mpc8xxx: Update DDR registers	2012-10-22 14:31:26 -05:00
mpc86xx	arch/powerpc/cpu/mpc86xx/cpu.c: Fix GCC 4.6 build warning	2011-12-02 00:16:46 +01:00
mpc512x	serial: Remove CONFIG_SERIAL_MULTI from serial drivers	2012-10-15 11:53:58 -07:00
mpc824x	mpc82xx: Remove BMW board port	2012-10-17 07:55:50 -07:00
mpc8220	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
mpc8260	serial: Use default_serial_puts() in drivers	2012-10-17 07:55:50 -07:00
ppc4xx	usb: lowlevel interface change to support multiple controllers	2012-10-15 11:54:00 -07:00