mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 12:28:52 +09:00
16fa00a711
Added usb dwc3 driver support for zynqmp this also supports the DFU and LTHOR to download the linux images on to RAM and cen be booted from those linux images. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
121 lines
2.8 KiB
C
121 lines
2.8 KiB
C
/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
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#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
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#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
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#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
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#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
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#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
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#define ZYNQ_SPI_BASEADDR0 0xFF040000
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#define ZYNQ_SPI_BASEADDR1 0xFF050000
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#define ZYNQ_I2C_BASEADDR0 0xFF020000
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#define ZYNQ_I2C_BASEADDR1 0xFF030000
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#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
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#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
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#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
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#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
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#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
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#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
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#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
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struct crlapb_regs {
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u32 reserved0[36];
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u32 cpu_r5_ctrl; /* 0x90 */
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u32 reserved1[37];
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u32 timestamp_ref_ctrl; /* 0x128 */
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u32 reserved2[53];
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u32 boot_mode; /* 0x200 */
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u32 reserved3[14];
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u32 rst_lpd_top; /* 0x23C */
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u32 reserved4[26];
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};
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#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
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#if defined(CONFIG_SECURE_IOU)
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#define ZYNQMP_IOU_SCNTR 0xFF260000
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#else
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#define ZYNQMP_IOU_SCNTR 0xFF250000
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#endif
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
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#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
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struct iou_scntr {
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u32 counter_control_register;
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u32 reserved0[7];
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u32 base_frequency_id_register;
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};
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#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
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/* Bootmode setting values */
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#define BOOT_MODES_MASK 0x0000000F
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#define SD_MODE 0x00000003
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#define EMMC_MODE 0x00000006
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#define JTAG_MODE 0x00000000
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#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
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struct iou_slcr_regs {
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u32 mio_pin[78];
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u32 reserved[442];
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};
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#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
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#define ZYNQMP_RPU_BASEADDR 0xFF9A0000
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struct rpu_regs {
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u32 rpu_glbl_ctrl;
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u32 reserved0[63];
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u32 rpu0_cfg; /* 0x100 */
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u32 reserved1[63];
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u32 rpu1_cfg; /* 0x200 */
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};
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#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
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#define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
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struct crfapb_regs {
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u32 reserved0[65];
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u32 rst_fpd_apu; /* 0x104 */
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u32 reserved1;
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};
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#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
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#define ZYNQMP_APU_BASEADDR 0xFD5C0000
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struct apu_regs {
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u32 reserved0[16];
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u32 rvbar_addr0_l; /* 0x40 */
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u32 rvbar_addr0_h; /* 0x44 */
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u32 reserved1[20];
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};
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#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
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/* Board version value */
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#define ZYNQMP_CSU_VERSION_SILICON 0x0
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#define ZYNQMP_CSU_VERSION_EP108 0x1
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#define ZYNQMP_CSU_VERSION_VELOCE 0x2
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#define ZYNQMP_CSU_VERSION_QEMU 0x3
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#endif /* _ASM_ARCH_HARDWARE_H */
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