mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 20:38:52 +09:00
79cf644e2d
Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
83 lines
3.4 KiB
C
83 lines
3.4 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _TEGRA124_MC_H_
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#define _TEGRA124_MC_H_
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/**
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* Defines the memory controller registers we need/care about
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*/
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struct mc_ctlr {
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u32 reserved0[4]; /* offset 0x00 - 0x0C */
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u32 mc_smmu_config; /* offset 0x10 */
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u32 mc_smmu_tlb_config; /* offset 0x14 */
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u32 mc_smmu_ptc_config; /* offset 0x18 */
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u32 mc_smmu_ptb_asid; /* offset 0x1C */
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u32 mc_smmu_ptb_data; /* offset 0x20 */
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u32 reserved1[3]; /* offset 0x24 - 0x2C */
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u32 mc_smmu_tlb_flush; /* offset 0x30 */
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u32 mc_smmu_ptc_flush; /* offset 0x34 */
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u32 reserved2[6]; /* offset 0x38 - 0x4C */
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u32 mc_emem_cfg; /* offset 0x50 */
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u32 mc_emem_adr_cfg; /* offset 0x54 */
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u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
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u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
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u32 reserved3[4]; /* offset 0x60 - 0x6C */
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u32 mc_security_cfg0; /* offset 0x70 */
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u32 mc_security_cfg1; /* offset 0x74 */
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u32 reserved4[6]; /* offset 0x7C - 0x8C */
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u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
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u32 reserved5[74]; /* offset 0x100 - 0x224 */
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u32 mc_smmu_translation_enable_0; /* offset 0x228 */
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u32 mc_smmu_translation_enable_1; /* offset 0x22C */
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u32 mc_smmu_translation_enable_2; /* offset 0x230 */
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u32 mc_smmu_translation_enable_3; /* offset 0x234 */
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u32 mc_smmu_afi_asid; /* offset 0x238 */
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u32 mc_smmu_avpc_asid; /* offset 0x23C */
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u32 mc_smmu_dc_asid; /* offset 0x240 */
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u32 mc_smmu_dcb_asid; /* offset 0x244 */
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u32 reserved6[2]; /* offset 0x248 - 0x24C */
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u32 mc_smmu_hc_asid; /* offset 0x250 */
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u32 mc_smmu_hda_asid; /* offset 0x254 */
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u32 mc_smmu_isp2_asid; /* offset 0x258 */
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u32 reserved7[2]; /* offset 0x25C - 0x260 */
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u32 mc_smmu_msenc_asid; /* offset 0x264 */
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u32 mc_smmu_nv_asid; /* offset 0x268 */
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u32 mc_smmu_nv2_asid; /* offset 0x26C */
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u32 mc_smmu_ppcs_asid; /* offset 0x270 */
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u32 mc_smmu_sata_asid; /* offset 0x274 */
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u32 reserved8[1]; /* offset 0x278 */
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u32 mc_smmu_vde_asid; /* offset 0x27C */
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u32 mc_smmu_vi_asid; /* offset 0x280 */
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u32 mc_smmu_vic_asid; /* offset 0x284 */
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u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
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u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
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u32 reserved9[1]; /* offset 0x290 */
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u32 mc_smmu_tsec_asid; /* offset 0x294 */
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u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
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u32 reserved10[235]; /* offset 0x29C - 0x644 */
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u32 mc_video_protect_bom; /* offset 0x648 */
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u32 mc_video_protect_size_mb; /* offset 0x64c */
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u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
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};
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#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
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#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
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#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
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#endif /* _TEGRA124_MC_H_ */
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