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https://github.com/brain-hackers/u-boot-brain
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![Stefan Roese](/assets/img/avatar_default.png)
On PPC44x platforms, the startup message generated in "cpu.c" only comprised the ppc type and revision but not additional informations like speed etc. Those speed infos where printed in the board specific code. This new implementation now prints all CPU infos in the common cpu specific code. No board specific code is needed anymore and therefore removed from all current 44x implementations. Patch by Stefan Roese, 27 Nov 2005
537 lines
18 KiB
C
537 lines
18 KiB
C
/*
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* Copyright (c) 2005
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* Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include "metrobox.h"
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#include "metrobox_version.h"
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include "../common/ppc440gx_i2c.h"
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#include "../common/sb_common.h"
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void fpga_init (void);
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METROBOX_BOARD_ID_ST board_id_as[] =
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{ {"Undefined"}, /* Not specified */
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{"2x10Gb"}, /* 2 ports, 10 GbE */
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{"20x1Gb"}, /* 20 ports, 1 GbE */
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{"Reserved"}, /* Reserved for future use */
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};
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/*************************************************************************
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* board_early_init_f
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*
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* Setup chip selects, initialize the Opto-FPGA, initialize
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* interrupt polarity and triggers.
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************************************************************************/
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int board_early_init_f (void)
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{
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ppc440_gpio_regs_t *gpio_regs;
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/* Enable GPIO interrupts */
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mtsdr(sdr_pfc0, 0x00103E00);
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/* Setup access for LEDs, and system topology info */
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gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
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gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
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gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
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/* Turn on all the leds for now */
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gpio_regs->out = SBCOMMON_GPIO_LEDS;
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/*--------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------*/
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mtebc(xbcfg,
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EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
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EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
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EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
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EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
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EBC_CFG_PR_32);
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/*--------------------------------------------------------------------+
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| 1/2 MB FLASH. Initialize bank 0 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb0ap,
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
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EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
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EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
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EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
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/*--------------------------------------------------------------------+
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| 8KB NVRAM/RTC. Initialize bank 1 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb1ap,
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
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EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
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EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
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EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
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/*--------------------------------------------------------------------+
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| Compact Flash, uses 2 Chip Selects (2 & 6)
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+-------------------------------------------------------------------*/
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mtebc(pb2ap,
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
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EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
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EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
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EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
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/*--------------------------------------------------------------------+
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| OPTO & OFEM FPGA. Initialize bank 3 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb3ap,
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EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
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EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
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mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*--------------------------------------------------------------------+
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| MAC A for metrobox
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| MAC A & B for Kamino. OFEM FPGA decodes the addresses
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| Initialize bank 4 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb4ap,
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EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
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EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
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mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*--------------------------------------------------------------------+
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| Metrobox MAC B Initialize bank 5 with default values.
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| KA REF FPGA Initialize bank 5 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb5ap,
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EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
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EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
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mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*--------------------------------------------------------------------+
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| Compact Flash, uses 2 Chip Selects (2 & 6)
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+-------------------------------------------------------------------*/
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mtebc(pb6ap,
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
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EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
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EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
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EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
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EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
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/*--------------------------------------------------------------------+
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| BME-32. Initialize bank 7 with default values.
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+-------------------------------------------------------------------*/
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mtebc(pb7ap,
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EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
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EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
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EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
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mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*--------------------------------------------------------------------+
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* Setup the interrupt controller polarities, triggers, etc.
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+-------------------------------------------------------------------*/
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000000); /* all non- critical */
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mtdcr (uic0pr, 0xfffffe03); /* polarity */
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mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
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mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic0sr, 0xffffffff); /* clear all */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000000); /* all non-critical */
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mtdcr (uic1pr, 0xffffc8ff); /* polarity */
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mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffff83ff); /* polarity */
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mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uicb0sr, 0xfc000000); /* clear all */
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mtdcr (uicb0er, 0x00000000); /* disable all */
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mtdcr (uicb0cr, 0x00000000); /* all non-critical */
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mtdcr (uicb0pr, 0xfc000000);
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mtdcr (uicb0tr, 0x00000000);
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mtdcr (uicb0vr, 0x00000001);
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fpga_init();
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return 0;
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}
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/*************************************************************************
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* checkboard
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*
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* Dump pertinent info to the console
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************************************************************************/
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int checkboard (void)
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{
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sys_info_t sysinfo;
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unsigned char brd_rev, brd_id;
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unsigned short sernum;
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unsigned char opto_rev, opto_id;
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OPTO_FPGA_REGS_ST *opto_ps;
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opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
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opto_rev = (unsigned char)((opto_ps->revision_ul &
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SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
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>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
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opto_id = (unsigned char)((opto_ps->revision_ul &
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SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
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>> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
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brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
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SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
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>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
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brd_id = (unsigned char)((opto_ps->boardinfo_ul &
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SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
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>> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
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get_sys_info (&sysinfo);
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sernum = sbcommon_get_serial_number();
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printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
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printf ("%s\n", METROBOX_U_BOOT_REL_STR);
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printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
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if (sbcommon_get_master()) {
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printf("Slot 0 - Master\nSlave board");
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if (sbcommon_secondary_present())
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printf(" present\n");
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else
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printf(" not detected\n");
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} else {
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printf("Slot 1 - Slave\n\n");
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}
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printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
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printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id]);
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/* Fix the ack in the bme 32 */
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udelay(5000);
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out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
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asm("eieio");
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return (0);
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}
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/*************************************************************************
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* misc_init_f
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*
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* Initialize I2C bus one to gain access to the fans
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************************************************************************/
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int misc_init_f (void)
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{
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/* Turn on i2c bus 1 */
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puts ("I2C1: ");
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i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
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puts ("ready\n");
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/* Turn on fans */
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sbcommon_fans();
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return (0);
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}
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/*************************************************************************
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* misc_init_r
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*
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* Do nothing.
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************************************************************************/
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int misc_init_r (void)
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{
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unsigned short sernum;
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char envstr[255];
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unsigned char opto_rev;
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OPTO_FPGA_REGS_ST *opto_ps;
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opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
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if(NULL != getenv("secondserial")) {
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puts("secondserial is set, switching to second serial port\n");
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setenv("stderr", "serial1");
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setenv("stdout", "serial1");
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setenv("stdin", "serial1");
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}
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setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
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memset(envstr, 0, 255);
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sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
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setenv("bldstr", envstr);
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saveenv();
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if( getenv("autorecover")) {
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setenv("autorecover", NULL);
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saveenv();
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sernum = sbcommon_get_serial_number();
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printf("\nSetting up environment for automatic filesystem recovery\n");
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/*
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* Setup default bootargs
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*/
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memset(envstr, 0, 255);
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sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
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"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
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sernum, sernum);
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setenv("bootargs", envstr);
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/*
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* Setup Default boot command
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*/
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setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
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"fatload ide 0 8100000 pramdisk;"
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"bootm 8000000 8100000");
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printf("Done. Please type allow the system to continue to boot\n");
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}
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if( getenv("fakeled")) {
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setenv("bootdelay", "-1");
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saveenv();
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printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
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opto_rev = (unsigned char)((opto_ps->revision_ul &
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SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
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>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
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if(0x12 <= opto_rev) {
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opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
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}
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}
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return (0);
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}
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/*************************************************************************
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* ide_set_reset
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************************************************************************/
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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OPTO_FPGA_REGS_ST *opto_ps;
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opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
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if (on) { /* assert RESET */
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opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
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} else { /* release RESET */
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opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
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}
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}
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#endif /* CONFIG_IDE_RESET */
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/*************************************************************************
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* fpga_init
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************************************************************************/
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void fpga_init(void)
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{
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OPTO_FPGA_REGS_ST *opto_ps;
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unsigned char opto_rev;
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unsigned long tmp;
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/* Ensure we have power all around */
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udelay(500);
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/*
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* Take appropriate hw bits out of reset
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*/
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opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
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tmp =
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SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
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SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
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SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
|
|
SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
|
|
opto_ps->reset_ul = tmp;
|
|
/*
|
|
* Turn on the 'Slow Blink' for the System Error Led.
|
|
* Ensure FPGA rev is up to at least rev 0x12
|
|
*/
|
|
opto_rev = (unsigned char)((opto_ps->revision_ul &
|
|
SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
|
|
>> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
|
|
if(0x12 <= opto_rev) {
|
|
opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
|
|
}
|
|
|
|
asm("eieio");
|
|
|
|
return;
|
|
}
|
|
|
|
int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
unsigned short sernum;
|
|
char envstr[255];
|
|
|
|
sernum = sbcommon_get_serial_number();
|
|
|
|
memset(envstr, 0, 255);
|
|
/*
|
|
* Setup our ip address
|
|
*/
|
|
sprintf(envstr, "10.100.60.%d", sernum);
|
|
|
|
setenv("ipaddr", envstr);
|
|
/*
|
|
* Setup the host ip address
|
|
*/
|
|
setenv("serverip", "10.100.17.10");
|
|
|
|
/*
|
|
* Setup default bootargs
|
|
*/
|
|
memset(envstr, 0, 255);
|
|
|
|
sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
|
|
"rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
|
|
"nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
|
|
":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
|
|
sernum, sernum, sernum);
|
|
|
|
setenv("bootargs_nfs", envstr);
|
|
setenv("bootargs", envstr);
|
|
|
|
/*
|
|
* Setup CF bootargs
|
|
*/
|
|
memset(envstr, 0, 255);
|
|
sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
|
|
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
|
|
sernum, sernum);
|
|
|
|
setenv("bootargs_cf", envstr);
|
|
|
|
/*
|
|
* Setup Default boot command
|
|
*/
|
|
setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
|
setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
|
|
|
|
/*
|
|
* Setup compact flash boot command
|
|
*/
|
|
setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
|
|
|
|
saveenv();
|
|
|
|
|
|
return(1);
|
|
}
|
|
|
|
int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
unsigned short sernum;
|
|
char envstr[255];
|
|
|
|
sernum = sbcommon_get_serial_number();
|
|
|
|
printf("\nSetting up environment for filesystem recovery\n");
|
|
/*
|
|
* Setup default bootargs
|
|
*/
|
|
memset(envstr, 0, 255);
|
|
sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
|
|
"rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
|
|
sernum, sernum);
|
|
|
|
setenv("bootargs", envstr);
|
|
|
|
/*
|
|
* Setup Default boot command
|
|
*/
|
|
setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
|
|
"fatload ide 0 8100000 pramdisk;"
|
|
"bootm 8000000 8100000");
|
|
|
|
printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
|
|
" please type fsrecover.sh<cr>\n");
|
|
|
|
return(1);
|
|
}
|
|
|
|
U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
|
|
"mbsetup - Set environment to factory defaults\n", NULL);
|
|
|
|
U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
|
|
"mbrecover - Set environment to allow for fs recovery\n", NULL);
|