u-boot-brain/arch/arm/dts/imx6q-b850v3.dts

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2015 Timesys Corporation.
 * Copyright 2015 General Electric Company
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/dts-v1/;

#include "imx6q-bx50v3.dtsi"

/ {
	model = "General Electric B850v3";
	compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";

	chosen {
		stdout-path = &uart3;
	};
};

&clks {
	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
			  <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
			  <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
				 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
};

&ldb {
	fsl,dual-channel;
	status = "okay";

	lvds0: lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <24>;
		status = "okay";

		port@4 {
			reg = <4>;

			lvds0_out: endpoint {
				remote-endpoint = <&stdp4028_in>;
			};
		};
	};
};

&i2c2 {
	pca9547_ddc: mux@70 {
		compatible = "nxp,pca9547";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;

		mux2_i2c1: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0>;
		};

		mux2_i2c2: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1>;
		};

		mux2_i2c3: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;
		};

		mux2_i2c4: i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;
		};

		mux2_i2c5: i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x4>;
		};

		mux2_i2c6: i2c@5 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x5>;
		};

		mux2_i2c7: i2c@6 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x6>;
		};

		mux2_i2c8: i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x7>;
		};
	};
};

&hdmi {
	ddc-i2c-bus = <&mux2_i2c1>;
};

&mux1_i2c1 {
	ads7830@4a {
		compatible = "ti,ads7830";
		reg = <0x4a>;
	};
};

&mux2_i2c2 {
	clock-frequency = <100000>;

	stdp2690@72 {
		compatible = "megachips,stdp2690-ge-b850v3-fw";
		reg = <0x72>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				stdp2690_in: endpoint {
					remote-endpoint = <&stdp4028_out>;
				};
			};

			port@1 {
				reg = <1>;

				stdp2690_out: endpoint {
					/* Connector for external display */
				};
			};
		};
	};

	stdp4028@73 {
		compatible = "megachips,stdp4028-ge-b850v3-fw";
		reg = <0x73>;
		interrupt-parent = <&gpio2>;
		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				stdp4028_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};

			port@1 {
				reg = <1>;

				stdp4028_out: endpoint {
					remote-endpoint = <&stdp2690_in>;
				};
			};
		};
	};
};

&pca9539 {
	P10 {
		gpio-hog;
		gpios = <8 0>;
		output-low;
		line-name = "PCA9539-P10";
	};

	P11 {
		gpio-hog;
		gpios = <9 0>;
		output-low;
		line-name = "PCA9539-P11";
	};
};

&pci_root {
	/* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
	bridge@1,0 {
		compatible = "pci10b5,8605";
		reg = <0x00010000 0 0 0 0>;

		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;

		bridge@2,1 {
			compatible = "pci10b5,8605";
			reg = <0x00020800 0 0 0 0>;

			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;

			/* Intel Corporation I210 Gigabit Network Connection */
			ethernet@3,0 {
				compatible = "pci8086,1533";
				reg = <0x00030000 0 0 0 0>;
			};
		};

		bridge@2,2 {
			compatible = "pci10b5,8605";
			reg = <0x00021000 0 0 0 0>;

			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;

			/* Intel Corporation I210 Gigabit Network Connection */
			switch_nic: ethernet@4,0 {
				compatible = "pci8086,1533";
				reg = <0x00040000 0 0 0 0>;
			};
		};
	};
};

&switch_ports {
	port@0 {
		reg = <0>;
		label = "eneport1";
		phy-handle = <&switchphy0>;
	};

	port@1 {
		reg = <1>;
		label = "eneport2";
		phy-handle = <&switchphy1>;
	};

	port@2 {
		reg = <2>;
		label = "enix";
		phy-handle = <&switchphy2>;
	};

	port@3 {
		reg = <3>;
		label = "enid";
		phy-handle = <&switchphy3>;
	};

	port@4 {
		reg = <4>;
		label = "cpu";
		ethernet = <&switch_nic>;
		phy-handle = <&switchphy4>;
	};
};