mirror of
https://github.com/brain-hackers/u-boot-brain
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6c59363004
Add exception handlers for generic and EJTAG exceptions. Most of the assembly code is imported from Linux kernel and adapted to U-Boot. The exception vector table will be reserved above the stack before U-Boot is relocated. The exception handlers will be installed and activated after relocation in the initr_traps hook function. Generic exceptions are handled by showing a CPU register dump similar to Linux kernel. For example: malta # md 1 00000001: Ooops: $ 0 : 00000000 00000000 00000009 00000004 $ 4 : 8ff7e108 00000000 0000003a 00000000 $ 8 : 00000008 00000001 8ff7cd18 00000004 $12 : 00000002 00000000 00000005 0000003a $16 : 00000004 00000040 00000001 00000001 $20 : 00000000 8fff53c0 00000008 00000004 $24 : ffffffff 8ffdea44 $28 : 90001650 8ff7cd00 00000004 8ffe6818 Hi : 00000000 Lo : 00000004 epc : 8ffe6848 (text bfc28848) ra : 8ffe6818 (text bfc28818) Status: 00000006 Cause : 00000410 (ExcCode 04) BadVA : 8ff9e928 PrId : 00019300 ### ERROR ### Please RESET the board ### EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler if necessary. Otherwise the debug mode will simply be exited. The SDBBP handler currently prints the contents of registers c0_depc and c0_debug. This could be extended in the future to handle semi-hosting according to the MIPS UHI specification. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Paul Burton <paul.burton@imgtec.com>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
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* Copyright (C) 1995, 1996 Paul M. Antoine
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* Copyright (C) 1998 Ulf Carlsson
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
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* Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2014, Imagination Technologies Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void show_regs(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned int cause = regs->cp0_cause;
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unsigned int exccode;
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int i;
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/*
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* Saved main processor registers
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*/
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for (i = 0; i < 32; ) {
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if ((i % 4) == 0)
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printf("$%2d :", i);
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if (i == 0)
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printf(" %0*lx", field, 0UL);
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else if (i == 26 || i == 27)
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printf(" %*s", field, "");
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else
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printf(" %0*lx", field, regs->regs[i]);
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i++;
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if ((i % 4) == 0)
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puts("\n");
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}
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printf("Hi : %0*lx\n", field, regs->hi);
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printf("Lo : %0*lx\n", field, regs->lo);
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/*
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* Saved cp0 registers
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*/
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printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
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field, regs->cp0_epc - gd->reloc_off);
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printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
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field, regs->regs[31] - gd->reloc_off);
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printf("Status: %08x\n", (uint32_t) regs->cp0_status);
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exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
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printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
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if (1 <= exccode && exccode <= 5)
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printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
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printf("PrId : %08x\n", read_c0_prid());
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}
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void do_reserved(const struct pt_regs *regs)
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{
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puts("\nOoops:\n");
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show_regs(regs);
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hang();
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}
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void do_ejtag_debug(const struct pt_regs *regs)
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{
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const int field = 2 * sizeof(unsigned long);
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unsigned long depc;
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unsigned int debug;
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depc = read_c0_depc();
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debug = read_c0_debug();
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printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
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field, depc, debug);
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}
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static void set_handler(unsigned long offset, void *addr, unsigned long size)
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{
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unsigned long ebase = gd->irq_sp;
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memcpy((void *)(ebase + offset), addr, size);
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flush_cache(ebase + offset, size);
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}
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void trap_init(ulong reloc_addr)
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{
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unsigned long ebase = gd->irq_sp;
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set_handler(0x180, &except_vec3_generic, 0x80);
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set_handler(0x280, &except_vec_ejtag_debug, 0x80);
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write_c0_ebase(ebase);
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clear_c0_status(ST0_BEV);
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execution_hazard_barrier();
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}
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