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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 13:58:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
564 lines
15 KiB
C
564 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Driver for AT91/AT32 MULTI LAYER LCD Controller
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*
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* Copyright (C) 2012 Atmel Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <clk.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <lcd.h>
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#include <video.h>
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#include <wait_bit.h>
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#include <atmel_hlcdc.h>
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#if defined(CONFIG_LCD_LOGO)
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#include <bmp_logo.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_DM_VIDEO
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/* configurable parameters */
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
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#define ATMEL_LCDC_DMA_BURST_LEN 8
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#ifndef ATMEL_LCDC_GUARD_TIME
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#define ATMEL_LCDC_GUARD_TIME 1
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#endif
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#define ATMEL_LCDC_FIFO_SIZE 512
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/*
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* the CLUT register map as following
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* RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
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*/
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
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{
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writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
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((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
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| ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
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| ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
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}
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ushort *configuration_get_cmap(void)
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{
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#if defined(CONFIG_LCD_LOGO)
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return bmp_logo_palette;
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#else
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return NULL;
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#endif
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}
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void lcd_ctrl_init(void *lcdbase)
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{
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unsigned long value;
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struct lcd_dma_desc *desc;
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struct atmel_hlcd_regs *regs;
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int ret;
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if (!has_lcdc())
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return; /* No lcdc */
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regs = (struct atmel_hlcd_regs *)panel_info.mmio;
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/* Disable DISP signal */
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writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable synchronization */
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writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable pixel clock */
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writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable PWM */
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writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Set pixel clock */
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value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
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if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
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value++;
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if (value < 1) {
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/* Using system clock as pixel clock */
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writel(LCDC_LCDCFG0_CLKDIV(0)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| panel_info.vl_clk_pol
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| LCDC_LCDCFG0_CLKSEL,
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®s->lcdc_lcdcfg0);
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} else {
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writel(LCDC_LCDCFG0_CLKDIV(value - 2)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| panel_info.vl_clk_pol,
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®s->lcdc_lcdcfg0);
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}
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/* Initialize control register 5 */
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value = 0;
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value |= panel_info.vl_sync;
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#ifndef LCD_OUTPUT_BPP
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/* Output is 24bpp */
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
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#else
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switch (LCD_OUTPUT_BPP) {
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case 12:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
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break;
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case 16:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
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break;
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case 18:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
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break;
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case 24:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
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break;
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default:
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BUG();
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break;
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}
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#endif
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value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
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value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
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writel(value, ®s->lcdc_lcdcfg5);
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/* Vertical & Horizontal Timing */
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value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
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value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
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writel(value, ®s->lcdc_lcdcfg1);
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value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
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value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
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writel(value, ®s->lcdc_lcdcfg2);
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value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
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value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
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writel(value, ®s->lcdc_lcdcfg3);
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/* Display size */
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value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
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value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
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writel(value, ®s->lcdc_lcdcfg4);
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writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
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®s->lcdc_basecfg0);
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switch (NBITS(panel_info.vl_bpix)) {
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case 16:
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writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
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®s->lcdc_basecfg1);
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break;
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case 32:
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writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
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®s->lcdc_basecfg1);
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break;
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default:
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BUG();
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break;
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}
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writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
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writel(0, ®s->lcdc_basecfg3);
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writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
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/* Disable all interrupts */
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writel(~0UL, ®s->lcdc_lcdidr);
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writel(~0UL, ®s->lcdc_baseidr);
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/* Setup the DMA descriptor, this descriptor will loop to itself */
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desc = (struct lcd_dma_desc *)(lcdbase - 16);
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desc->address = (u32)lcdbase;
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/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
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desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
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| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
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desc->next = (u32)desc;
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/* Flush the DMA descriptor if we enabled dcache */
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flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
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writel(desc->address, ®s->lcdc_baseaddr);
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writel(desc->control, ®s->lcdc_basectrl);
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writel(desc->next, ®s->lcdc_basenext);
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writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
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®s->lcdc_basecher);
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/* Enable LCD */
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value = readl(®s->lcdc_lcden);
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writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
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true, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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value = readl(®s->lcdc_lcden);
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writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
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true, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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value = readl(®s->lcdc_lcden);
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writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
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true, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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value = readl(®s->lcdc_lcden);
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writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
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true, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Enable flushing if we enabled dcache */
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lcd_set_flush_dcache(1);
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}
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#else
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enum {
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LCD_MAX_WIDTH = 1024,
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LCD_MAX_HEIGHT = 768,
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LCD_MAX_LOG2_BPP = VIDEO_BPP16,
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};
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struct atmel_hlcdc_priv {
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struct atmel_hlcd_regs *regs;
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struct display_timing timing;
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unsigned int vl_bpix;
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unsigned int output_mode;
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unsigned int guard_time;
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ulong clk_rate;
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};
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static int at91_hlcdc_enable_clk(struct udevice *dev)
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{
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struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
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struct clk clk;
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ulong clk_rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return -EINVAL;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk);
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if (!clk_rate) {
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clk_disable(&clk);
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return -ENODEV;
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}
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priv->clk_rate = clk_rate;
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clk_free(&clk);
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return 0;
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}
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static void atmel_hlcdc_init(struct udevice *dev)
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{
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
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struct atmel_hlcd_regs *regs = priv->regs;
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struct display_timing *timing = &priv->timing;
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struct lcd_dma_desc *desc;
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unsigned long value, vl_clk_pol;
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int ret;
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/* Disable DISP signal */
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writel(LCDC_LCDDIS_DISPDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable synchronization */
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writel(LCDC_LCDDIS_SYNCDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable pixel clock */
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writel(LCDC_LCDDIS_CLKDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Disable PWM */
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writel(LCDC_LCDDIS_PWMDIS, ®s->lcdc_lcddis);
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ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
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false, 1000, false);
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if (ret)
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printf("%s: %d: Timeout!\n", __func__, __LINE__);
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/* Set pixel clock */
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value = priv->clk_rate / timing->pixelclock.typ;
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if (priv->clk_rate % timing->pixelclock.typ)
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value++;
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vl_clk_pol = 0;
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if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
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vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
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if (value < 1) {
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/* Using system clock as pixel clock */
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writel(LCDC_LCDCFG0_CLKDIV(0)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| vl_clk_pol
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| LCDC_LCDCFG0_CLKSEL,
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®s->lcdc_lcdcfg0);
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} else {
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writel(LCDC_LCDCFG0_CLKDIV(value - 2)
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| LCDC_LCDCFG0_CGDISHCR
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| LCDC_LCDCFG0_CGDISHEO
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| LCDC_LCDCFG0_CGDISOVR1
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| LCDC_LCDCFG0_CGDISBASE
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| vl_clk_pol,
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®s->lcdc_lcdcfg0);
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}
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/* Initialize control register 5 */
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value = 0;
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if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
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value |= LCDC_LCDCFG5_HSPOL;
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if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
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value |= LCDC_LCDCFG5_VSPOL;
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switch (priv->output_mode) {
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case 12:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
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break;
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case 16:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
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break;
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case 18:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
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break;
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case 24:
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
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break;
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default:
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BUG();
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break;
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}
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value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
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value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
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writel(value, ®s->lcdc_lcdcfg5);
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/* Vertical & Horizontal Timing */
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value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
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value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
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writel(value, ®s->lcdc_lcdcfg1);
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value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
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value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
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writel(value, ®s->lcdc_lcdcfg2);
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value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
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value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
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writel(value, ®s->lcdc_lcdcfg3);
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/* Display size */
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value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
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value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
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writel(value, ®s->lcdc_lcdcfg4);
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writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
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®s->lcdc_basecfg0);
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switch (VNBITS(priv->vl_bpix)) {
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case 16:
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writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
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®s->lcdc_basecfg1);
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break;
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case 32:
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writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
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®s->lcdc_basecfg1);
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break;
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default:
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BUG();
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break;
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}
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writel(LCDC_BASECFG2_XSTRIDE(0), ®s->lcdc_basecfg2);
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writel(0, ®s->lcdc_basecfg3);
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writel(LCDC_BASECFG4_DMA, ®s->lcdc_basecfg4);
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/* Disable all interrupts */
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writel(~0UL, ®s->lcdc_lcdidr);
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writel(~0UL, ®s->lcdc_baseidr);
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/* Setup the DMA descriptor, this descriptor will loop to itself */
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desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
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if (!desc)
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return;
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desc->address = (u32)uc_plat->base;
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/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
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desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
|
|
| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
|
|
desc->next = (u32)desc;
|
|
|
|
/* Flush the DMA descriptor if we enabled dcache */
|
|
flush_dcache_range((u32)desc,
|
|
ALIGN(((u32)desc + sizeof(*desc)),
|
|
CONFIG_SYS_CACHELINE_SIZE));
|
|
|
|
writel(desc->address, ®s->lcdc_baseaddr);
|
|
writel(desc->control, ®s->lcdc_basectrl);
|
|
writel(desc->next, ®s->lcdc_basenext);
|
|
writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
|
|
®s->lcdc_basecher);
|
|
|
|
/* Enable LCD */
|
|
value = readl(®s->lcdc_lcden);
|
|
writel(value | LCDC_LCDEN_CLKEN, ®s->lcdc_lcden);
|
|
ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
|
|
true, 1000, false);
|
|
if (ret)
|
|
printf("%s: %d: Timeout!\n", __func__, __LINE__);
|
|
value = readl(®s->lcdc_lcden);
|
|
writel(value | LCDC_LCDEN_SYNCEN, ®s->lcdc_lcden);
|
|
ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
|
|
true, 1000, false);
|
|
if (ret)
|
|
printf("%s: %d: Timeout!\n", __func__, __LINE__);
|
|
value = readl(®s->lcdc_lcden);
|
|
writel(value | LCDC_LCDEN_DISPEN, ®s->lcdc_lcden);
|
|
ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
|
|
true, 1000, false);
|
|
if (ret)
|
|
printf("%s: %d: Timeout!\n", __func__, __LINE__);
|
|
value = readl(®s->lcdc_lcden);
|
|
writel(value | LCDC_LCDEN_PWMEN, ®s->lcdc_lcden);
|
|
ret = wait_for_bit_le32(®s->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
|
|
true, 1000, false);
|
|
if (ret)
|
|
printf("%s: %d: Timeout!\n", __func__, __LINE__);
|
|
}
|
|
|
|
static int atmel_hlcdc_probe(struct udevice *dev)
|
|
{
|
|
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
ret = at91_hlcdc_enable_clk(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
atmel_hlcdc_init(dev);
|
|
|
|
uc_priv->xsize = priv->timing.hactive.typ;
|
|
uc_priv->ysize = priv->timing.vactive.typ;
|
|
uc_priv->bpix = priv->vl_bpix;
|
|
|
|
/* Enable flushing if we enabled dcache */
|
|
video_set_flush_dcache(dev, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
|
|
const void *blob = gd->fdt_blob;
|
|
int node = dev_of_offset(dev);
|
|
|
|
priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
|
|
if (!priv->regs) {
|
|
debug("%s: No display controller address\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
|
|
0, &priv->timing)) {
|
|
debug("%s: Failed to decode display timing\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
|
|
priv->timing.hactive.typ = LCD_MAX_WIDTH;
|
|
|
|
if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
|
|
priv->timing.vactive.typ = LCD_MAX_HEIGHT;
|
|
|
|
priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
|
|
if (!priv->vl_bpix) {
|
|
debug("%s: Failed to get bits per pixel\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
|
|
priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_hlcdc_bind(struct udevice *dev)
|
|
{
|
|
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
|
|
|
|
uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
|
(1 << LCD_MAX_LOG2_BPP) / 8;
|
|
|
|
debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id atmel_hlcdc_ids[] = {
|
|
{ .compatible = "atmel,sama5d2-hlcdc" },
|
|
{ .compatible = "atmel,at91sam9x5-hlcdc" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(atmel_hlcdfb) = {
|
|
.name = "atmel_hlcdfb",
|
|
.id = UCLASS_VIDEO,
|
|
.of_match = atmel_hlcdc_ids,
|
|
.bind = atmel_hlcdc_bind,
|
|
.probe = atmel_hlcdc_probe,
|
|
.ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
|
|
};
|
|
|
|
#endif
|