mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-30 23:03:45 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*/
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#ifndef _SYSTEM_MANAGER_H_
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#define _SYSTEM_MANAGER_H_
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
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#define SYSMGR_ECC_OCRAM_EN BIT(0)
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#define SYSMGR_ECC_OCRAM_SERR BIT(3)
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#define SYSMGR_ECC_OCRAM_DERR BIT(4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_SPIM0 BIT(0)
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#define SYSMGR_FPGAINTF_SPIM1 BIT(1)
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#define SYSMGR_FPGAINTF_EMAC0 BIT(2)
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#define SYSMGR_FPGAINTF_EMAC1 BIT(3)
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#define SYSMGR_FPGAINTF_NAND BIT(4)
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#define SYSMGR_FPGAINTF_SDMMC BIT(5)
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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/* For dedicated IO configuration */
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/* Voltage select enums */
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#define VOLTAGE_SEL_3V 0x0
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#define VOLTAGE_SEL_1P8V 0x1
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#define VOLTAGE_SEL_2P5V 0x2
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/* Input buffer enable */
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#define INPUT_BUF_DISABLE 0
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#define INPUT_BUF_1P8V 1
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#define INPUT_BUF_2P5V3V 2
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/* Weak pull up enable */
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#define WK_PU_DISABLE 0
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#define WK_PU_ENABLE 1
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/* Pull up slew rate control */
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#define PU_SLW_RT_SLOW 0
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#define PU_SLW_RT_FAST 1
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#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
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/* Pull down slew rate control */
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#define PD_SLW_RT_SLOW 0
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#define PD_SLW_RT_FAST 1
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#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
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/* Drive strength control */
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#define PU_DRV_STRG_DEFAULT 0x10
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#define PD_DRV_STRG_DEFAULT 0x10
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/* bit position */
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#define PD_DRV_STRG_LSB 0
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#define PD_SLW_RT_LSB 5
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#define PU_DRV_STRG_LSB 8
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#define PU_SLW_RT_LSB 13
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#define WK_PU_LSB 16
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#define INPUT_BUF_LSB 17
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#define BIAS_TRIM_LSB 19
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#define VOLTAGE_SEL_LSB 0
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#define ALT_SYSMGR_NOC_H2F_SET_MSK BIT(0)
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#define ALT_SYSMGR_NOC_LWH2F_SET_MSK BIT(4)
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#define ALT_SYSMGR_NOC_F2H_SET_MSK BIT(8)
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#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK BIT(16)
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#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK BIT(20)
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#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK BIT(24)
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#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK BIT(0)
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#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1)
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#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1)
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/system_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/system_manager_arria10.h>
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#endif
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#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
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(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
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#endif /* _SYSTEM_MANAGER_H_ */
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