York Sun 564e9383e5 drivers/ddr/fsl: Add calculation of register control words ... DDR4 RDIMM has some information in SPD to be used to calculate the control words for register chip. The rest can be found from JEDEC spec DDR4RCD02. Signed-off-by: York Sun <york.sun@nxp.com>		2018-01-30 09:14:07 -08:00
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altera	ddr: altera: silence PHY calibration unless in debug mode	2018-01-25 09:59:37 +01:00
fsl	drivers/ddr/fsl: Add calculation of register control words	2018-01-30 09:14:07 -08:00
marvell	ddr: marvell: update ddr controller init and freq	2018-01-19 16:30:29 +01:00
microchip	wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2018-01-24 12:03:43 +05:30
Kconfig	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00