mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
98f705c9ce
There was for long time no activity in the 4xx area. We need to go further and convert to Kconfig, but it turned out, nobody is interested anymore in 4xx, so remove it. Signed-off-by: Heiko Schocher <hs@denx.de>
308 lines
8.6 KiB
C
308 lines
8.6 KiB
C
/*
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* Xilinx xps_ll_temac ethernet driver for u-boot
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*
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* SDMA sub-controller
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*
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* Copyright (C) 2011 - 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (C) 2008 - 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008 - 2011 PetaLogix
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*
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* Based on Yoshio Kashiwagi kashiwagi@co-nss.co.jp driver
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* Copyright (C) 2008 Nissin Systems Co.,Ltd.
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* March 2008 created
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*
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* CREDITS: tsec driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [M]: [0]/ip_documentation/mpmc.pdf
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* [S]: [0]/ip_documentation/xps_ll_temac.pdf
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* [A]: [0]/application_notes/xapp1041.pdf
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*/
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#include <config.h>
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#include <common.h>
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#include <net.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include "xilinx_ll_temac.h"
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#include "xilinx_ll_temac_sdma.h"
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#define TX_BUF_CNT 2
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static unsigned int rx_idx; /* index of the current RX buffer */
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static unsigned int tx_idx; /* index of the current TX buffer */
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struct rtx_cdmac_bd {
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struct cdmac_bd rx[PKTBUFSRX];
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struct cdmac_bd tx[TX_BUF_CNT];
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};
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/*
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* DMA Buffer Descriptor alignment
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*
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* If the address contained in the Next Descriptor Pointer register is not
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* 8-word aligned or reaches beyond the range of available memory, the SDMA
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* halts processing and sets the CDMAC_BD_STCTRL_ERROR bit in the respective
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* status register (tx_chnl_sts or rx_chnl_sts).
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*
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* [1]: [0]/ip_documentation/mpmc.pdf
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* page 161, Next Descriptor Pointer
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*/
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static struct rtx_cdmac_bd cdmac_bd __aligned(32);
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/* Xilinx Processor Local Bus (PLB) in/out accessors */
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inline unsigned ll_temac_xlplb_in32(phys_addr_t addr)
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{
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return in_be32((void *)addr);
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}
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inline void ll_temac_xlplb_out32(phys_addr_t addr, unsigned value)
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{
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out_be32((void *)addr, value);
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}
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/* collect all register addresses for Xilinx PLB in/out accessors */
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void ll_temac_collect_xlplb_sdma_reg_addr(struct eth_device *dev)
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{
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struct ll_temac *ll_temac = dev->priv;
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struct sdma_ctrl *sdma_ctrl = (void *)ll_temac->ctrladdr;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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ra[TX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_nxtdesc_ptr;
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ra[TX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->tx_curbuf_addr;
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ra[TX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->tx_curbuf_length;
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ra[TX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_curdesc_ptr;
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ra[TX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->tx_taildesc_ptr;
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ra[TX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->tx_chnl_ctrl;
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ra[TX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->tx_irq_reg;
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ra[TX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->tx_chnl_sts;
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ra[RX_NXTDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_nxtdesc_ptr;
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ra[RX_CURBUF_ADDR] = (phys_addr_t)&sdma_ctrl->rx_curbuf_addr;
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ra[RX_CURBUF_LENGTH] = (phys_addr_t)&sdma_ctrl->rx_curbuf_length;
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ra[RX_CURDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_curdesc_ptr;
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ra[RX_TAILDESC_PTR] = (phys_addr_t)&sdma_ctrl->rx_taildesc_ptr;
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ra[RX_CHNL_CTRL] = (phys_addr_t)&sdma_ctrl->rx_chnl_ctrl;
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ra[RX_IRQ_REG] = (phys_addr_t)&sdma_ctrl->rx_irq_reg;
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ra[RX_CHNL_STS] = (phys_addr_t)&sdma_ctrl->rx_chnl_sts;
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ra[DMA_CONTROL_REG] = (phys_addr_t)&sdma_ctrl->dma_control_reg;
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}
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/* Check for TX and RX channel errors. */
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static inline int ll_temac_sdma_error(struct eth_device *dev)
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{
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int err;
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struct ll_temac *ll_temac = dev->priv;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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err = ll_temac->in32(ra[TX_CHNL_STS]) & CHNL_STS_ERROR;
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err |= ll_temac->in32(ra[RX_CHNL_STS]) & CHNL_STS_ERROR;
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return err;
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}
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int ll_temac_init_sdma(struct eth_device *dev)
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{
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struct ll_temac *ll_temac = dev->priv;
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struct cdmac_bd *rx_dp;
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struct cdmac_bd *tx_dp;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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int i;
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printf("%s: SDMA: %d Rx buffers, %d Tx buffers\n",
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dev->name, PKTBUFSRX, TX_BUF_CNT);
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/* Initialize the Rx Buffer descriptors */
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for (i = 0; i < PKTBUFSRX; i++) {
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rx_dp = &cdmac_bd.rx[i];
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memset(rx_dp, 0, sizeof(*rx_dp));
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rx_dp->next_p = rx_dp;
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rx_dp->buf_len = PKTSIZE_ALIGN;
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rx_dp->phys_buf_p = (u8 *)net_rx_packets[i];
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flush_cache((u32)rx_dp->phys_buf_p, PKTSIZE_ALIGN);
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}
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flush_cache((u32)cdmac_bd.rx, sizeof(cdmac_bd.rx));
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/* Initialize the TX Buffer Descriptors */
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for (i = 0; i < TX_BUF_CNT; i++) {
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tx_dp = &cdmac_bd.tx[i];
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memset(tx_dp, 0, sizeof(*tx_dp));
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tx_dp->next_p = tx_dp;
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}
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flush_cache((u32)cdmac_bd.tx, sizeof(cdmac_bd.tx));
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/* Reset index counter to the Rx and Tx Buffer descriptors */
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rx_idx = tx_idx = 0;
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/* initial Rx DMA start by writing to respective TAILDESC_PTR */
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ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
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ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
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return 0;
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}
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int ll_temac_halt_sdma(struct eth_device *dev)
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{
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unsigned timeout = 50; /* 1usec * 50 = 50usec */
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struct ll_temac *ll_temac = dev->priv;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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/*
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* Soft reset the DMA
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*
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* Quote from MPMC documentation: Writing a 1 to this field
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* forces the DMA engine to shutdown and reset itself. After
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* setting this bit, software must poll it until the bit is
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* cleared by the DMA. This indicates that the reset process
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* is done and the pipeline has been flushed.
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*/
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ll_temac->out32(ra[DMA_CONTROL_REG], DMA_CONTROL_RESET);
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while (timeout && (ll_temac->in32(ra[DMA_CONTROL_REG])
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& DMA_CONTROL_RESET)) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return -1;
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}
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return 0;
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}
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int ll_temac_reset_sdma(struct eth_device *dev)
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{
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u32 r;
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struct ll_temac *ll_temac = dev->priv;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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/* Soft reset the DMA. */
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if (ll_temac_halt_sdma(dev))
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return -1;
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/* Now clear the interrupts. */
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r = ll_temac->in32(ra[TX_CHNL_CTRL]);
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r &= ~CHNL_CTRL_IRQ_MASK;
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ll_temac->out32(ra[TX_CHNL_CTRL], r);
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r = ll_temac->in32(ra[RX_CHNL_CTRL]);
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r &= ~CHNL_CTRL_IRQ_MASK;
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ll_temac->out32(ra[RX_CHNL_CTRL], r);
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/* Now ACK pending IRQs. */
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ll_temac->out32(ra[TX_IRQ_REG], IRQ_REG_IRQ_MASK);
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ll_temac->out32(ra[RX_IRQ_REG], IRQ_REG_IRQ_MASK);
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/* Set tail-ptr mode, disable errors for both channels. */
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ll_temac->out32(ra[DMA_CONTROL_REG],
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/* Enable use of tail pointer register */
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DMA_CONTROL_TPE |
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/* Disable error when 2 or 4 bit coalesce cnt overfl */
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DMA_CONTROL_RXOCEID |
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/* Disable error when 2 or 4 bit coalesce cnt overfl */
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DMA_CONTROL_TXOCEID);
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return 0;
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}
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int ll_temac_recv_sdma(struct eth_device *dev)
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{
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int length, pb_idx;
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struct cdmac_bd *rx_dp = &cdmac_bd.rx[rx_idx];
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struct ll_temac *ll_temac = dev->priv;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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if (ll_temac_sdma_error(dev)) {
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if (ll_temac_reset_sdma(dev))
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return -1;
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ll_temac_init_sdma(dev);
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}
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flush_cache((u32)rx_dp, sizeof(*rx_dp));
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if (!(rx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED))
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return 0;
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if (rx_dp->sca.stctrl & (CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP)) {
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pb_idx = rx_idx;
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length = rx_dp->sca.app[4] & CDMAC_BD_APP4_RXBYTECNT_MASK;
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} else {
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pb_idx = -1;
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length = 0;
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printf("%s: Got part of package, unsupported (%x)\n",
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__func__, rx_dp->sca.stctrl);
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}
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/* flip the buffer */
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flush_cache((u32)rx_dp->phys_buf_p, length);
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/* reset the current descriptor */
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rx_dp->sca.stctrl = 0;
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rx_dp->sca.app[4] = 0;
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flush_cache((u32)rx_dp, sizeof(*rx_dp));
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/* Find next empty buffer descriptor, preparation for next iteration */
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rx_idx = (rx_idx + 1) % PKTBUFSRX;
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rx_dp = &cdmac_bd.rx[rx_idx];
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flush_cache((u32)rx_dp, sizeof(*rx_dp));
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/* DMA start by writing to respective TAILDESC_PTR */
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ll_temac->out32(ra[RX_CURDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
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ll_temac->out32(ra[RX_TAILDESC_PTR], (int)&cdmac_bd.rx[rx_idx]);
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if (length > 0 && pb_idx != -1)
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net_process_received_packet(net_rx_packets[pb_idx], length);
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return 0;
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}
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int ll_temac_send_sdma(struct eth_device *dev, void *packet, int length)
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{
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unsigned timeout = 50; /* 1usec * 50 = 50usec */
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struct cdmac_bd *tx_dp = &cdmac_bd.tx[tx_idx];
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struct ll_temac *ll_temac = dev->priv;
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phys_addr_t *ra = ll_temac->sdma_reg_addr;
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if (ll_temac_sdma_error(dev)) {
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if (ll_temac_reset_sdma(dev))
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return -1;
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ll_temac_init_sdma(dev);
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}
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tx_dp->phys_buf_p = (u8 *)packet;
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tx_dp->buf_len = length;
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tx_dp->sca.stctrl = CDMAC_BD_STCTRL_SOP | CDMAC_BD_STCTRL_EOP |
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CDMAC_BD_STCTRL_STOP_ON_END;
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flush_cache((u32)packet, length);
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flush_cache((u32)tx_dp, sizeof(*tx_dp));
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/* DMA start by writing to respective TAILDESC_PTR */
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ll_temac->out32(ra[TX_CURDESC_PTR], (int)tx_dp);
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ll_temac->out32(ra[TX_TAILDESC_PTR], (int)tx_dp);
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/* Find next empty buffer descriptor, preparation for next iteration */
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tx_idx = (tx_idx + 1) % TX_BUF_CNT;
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tx_dp = &cdmac_bd.tx[tx_idx];
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do {
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flush_cache((u32)tx_dp, sizeof(*tx_dp));
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udelay(1);
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} while (timeout-- && !(tx_dp->sca.stctrl & CDMAC_BD_STCTRL_COMPLETED));
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return -1;
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}
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return 0;
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}
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