York Sun 5605dc6135 drivers/ddr/fsl: Fix timing_cfg_2 register ... Commit 34e026f9 added one extra bit to wr_lat for timing_cfg_2, but with wrong bit position. It is bit 13 in big-endian, or left shift 18 from LSB. This error hasn't had any impact because we don't have fast enough DDR4 using the extra bit so far. Signed-off-by: York Sun <york.sun@nxp.com>		2016-06-03 14:12:06 -07:00
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altera	ddr: altera: Repair DQ window centering code	2016-04-20 11:28:45 +02:00
fsl	drivers/ddr/fsl: Fix timing_cfg_2 register	2016-06-03 14:12:06 -07:00
marvell	arm: mvebu: a38x: Weed out floating point use	2016-05-20 11:01:00 +02:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00