mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
175f502734
The ATF can pass additional information via the first four registers, x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer to a device tree with platform information. Parse this device tree and extract DRAM size information from it. This is useful on systems where the DRAM size can vary between configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
102 lines
2.1 KiB
C
102 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/ebisu/ebisu.c
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* This file is Ebisu board support.
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*
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* Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <dm.h>
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#include <dm/platform_data/serial_sh.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/rcar-mstp.h>
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#include <asm/arch/sh_sdhi.h>
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#include <i2c.h>
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#include <mmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void)
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{
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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return 0;
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}
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/*
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* If the firmware passed a device tree use it for U-Boot DRAM setup.
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*/
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extern u64 rcar_atf_boot_args[];
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int dram_init(void)
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{
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const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
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const void *blob;
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/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
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if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
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blob = atf_fdt_blob;
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else
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blob = gd->fdt_blob;
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return fdtdec_setup_mem_size_base_fdt(blob);
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}
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int dram_init_banksize(void)
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{
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const void *atf_fdt_blob = (const void *)(rcar_atf_boot_args[1]);
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const void *blob;
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/* Check if ATF passed us DTB. If not, fall back to builtin DTB. */
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if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
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blob = atf_fdt_blob;
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else
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blob = gd->fdt_blob;
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fdtdec_setup_memory_banksize_fdt(blob);
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return 0;
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}
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_RSTOUTCR (RST_BASE + 0x58)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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void reset_cpu(ulong addr)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else if (cputype == 0xd07)
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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else
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hang();
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}
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