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![Nobuhiro Iwamatsu](/assets/img/avatar_default.png)
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
681 lines
16 KiB
C
681 lines
16 KiB
C
/*
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* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
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*
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (c) 2008 Nobuhiro Iwamatsu
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include "sh_eth.h"
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#ifndef CONFIG_SH_ETHER_USE_PORT
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# error "Please define CONFIG_SH_ETHER_USE_PORT"
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#endif
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#ifndef CONFIG_SH_ETHER_PHY_ADDR
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# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
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#endif
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#define SH_ETH_PHY_DELAY 50000
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/*
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* Bits are written to the PHY serially using the
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* PIR register, just like a bit banger.
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*/
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static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
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{
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int i;
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u32 pir;
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/* Bit positions is 1 less than the number of bits */
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for (i = len - 1; i >= 0; i--) {
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/* Write direction, bit to write, clock is low */
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pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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/* Write direction, bit to write, clock is high */
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pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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/* Write direction, bit to write, clock is low */
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pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
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outl(pir, PIR(port));
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udelay(1);
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}
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}
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static void sh_eth_mii_bus_release(int port)
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{
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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/* Read direction, clock is high */
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outl(1, PIR(port));
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udelay(1);
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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static void sh_eth_mii_ind_bus_release(int port)
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{
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
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{
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int i;
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u32 pir;
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*val = 0;
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for (i = len - 1; i >= 0; i--) {
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/* Read direction, clock is high */
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outl(1, PIR(port));
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udelay(1);
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/* Read bit */
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pir = inl(PIR(port));
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*val |= (pir & 8) ? 1 << i : 0;
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/* Read direction, clock is low */
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outl(0, PIR(port));
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udelay(1);
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}
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}
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#define PHY_INIT 0xFFFFFFFF
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#define PHY_READ 0x02
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#define PHY_WRITE 0x01
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/*
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* To read a phy register, mii managements frames are sent to the phy.
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* The frames look like this:
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* pre (32 bits): 0xffff ffff
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* st (2 bits): 01
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* op (2bits): 10: read 01: write
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* phyad (5 bits): xxxxx
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* regad (5 bits): xxxxx
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* ta (Bus release):
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* data (16 bits): read data
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*/
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static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
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{
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u32 val;
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/* Sent mii management frame */
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/* pre */
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sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
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/* st (start of frame) */
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sh_eth_mii_write_phy_bits(port, 0x1, 2);
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/* op (code) */
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sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
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/* phy address */
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sh_eth_mii_write_phy_bits(port, phy_addr, 5);
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/* Register to read */
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sh_eth_mii_write_phy_bits(port, reg, 5);
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/* Bus release */
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sh_eth_mii_bus_release(port);
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/* Read register */
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sh_eth_mii_read_phy_bits(port, &val, 16);
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return val;
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}
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/*
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* To write a phy register, mii managements frames are sent to the phy.
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* The frames look like this:
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* pre (32 bits): 0xffff ffff
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* st (2 bits): 01
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* op (2bits): 10: read 01: write
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* phyad (5 bits): xxxxx
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* regad (5 bits): xxxxx
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* ta (2 bits): 10
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* data (16 bits): write data
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* idle (Independent bus release)
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*/
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static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
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{
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/* Sent mii management frame */
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/* pre */
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sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
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/* st (start of frame) */
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sh_eth_mii_write_phy_bits(port, 0x1, 2);
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/* op (code) */
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sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
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/* phy address */
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sh_eth_mii_write_phy_bits(port, phy_addr, 5);
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/* Register to read */
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sh_eth_mii_write_phy_bits(port, reg, 5);
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/* ta */
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sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
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/* Write register data */
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sh_eth_mii_write_phy_bits(port, val, 16);
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/* Independent bus release */
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sh_eth_mii_ind_bus_release(port);
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}
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int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
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{
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struct sh_eth_dev *eth = dev->priv;
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int port = eth->port, ret = 0, timeout;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (!packet || len > 0xffff) {
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printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
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ret = -EINVAL;
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goto err;
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}
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/* packet must be a 4 byte boundary */
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if ((int)packet & (4 - 1)) {
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printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
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ret = -EFAULT;
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goto err;
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}
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/* Update tx descriptor */
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port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
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port_info->tx_desc_cur->td1 = len << 16;
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/* Must preserve the end of descriptor list indication */
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if (port_info->tx_desc_cur->td0 & TD_TDLE)
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
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else
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
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/* Restart the transmitter if disabled */
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if (!(inl(EDTRR(port)) & EDTRR_TRNS))
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outl(EDTRR_TRNS, EDTRR(port));
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/* Wait until packet is transmitted */
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timeout = 1000;
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while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
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udelay(100);
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if (timeout < 0) {
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printf(SHETHER_NAME ": transmit timeout\n");
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ret = -ETIMEDOUT;
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goto err;
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}
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port_info->tx_desc_cur++;
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if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
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port_info->tx_desc_cur = port_info->tx_desc_base;
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return ret;
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err:
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return ret;
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}
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int sh_eth_recv(struct eth_device *dev)
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{
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struct sh_eth_dev *eth = dev->priv;
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int port = eth->port, len = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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volatile u8 *packet;
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/* Check if the rx descriptor is ready */
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if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
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/* Check for errors */
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if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
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len = port_info->rx_desc_cur->rd1 & 0xffff;
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packet = (volatile u8 *)
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ADDR_TO_P2(port_info->rx_desc_cur->rd2);
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NetReceive(packet, len);
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}
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/* Make current descriptor available again */
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if (port_info->rx_desc_cur->rd0 & RD_RDLE)
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port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
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else
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port_info->rx_desc_cur->rd0 = RD_RACT;
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/* Point to the next descriptor */
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port_info->rx_desc_cur++;
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if (port_info->rx_desc_cur >=
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port_info->rx_desc_base + NUM_RX_DESC)
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port_info->rx_desc_cur = port_info->rx_desc_base;
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}
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/* Restart the receiver if disabled */
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if (!(inl(EDRRR(port)) & EDRRR_R))
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outl(EDRRR_R, EDRRR(port));
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return len;
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}
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#define EDMR_INIT_CNT 1000
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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outl(EDSR_ENALL, EDSR(port));
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/* Perform a software reset and wait for it to complete */
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outl(EDMR_SRST, EDMR(port));
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for (i = 0; i < EDMR_INIT_CNT; i++) {
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if (!(inl(EDMR(port)) & EDMR_SRST))
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break;
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udelay(1000);
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}
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if (i == EDMR_INIT_CNT) {
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printf(SHETHER_NAME ": Software reset timeout\n");
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ret = -EIO;
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}
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return ret;
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}
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static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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{
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int port = eth->port, i, ret = 0;
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u32 tmp_addr;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct tx_desc_s *cur_tx_desc;
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/*
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* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
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*/
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port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
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sizeof(struct tx_desc_s) +
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TX_DESC_SIZE - 1);
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if (!port_info->tx_desc_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err;
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}
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tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
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~(TX_DESC_SIZE - 1));
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
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port_info->tx_desc_cur = port_info->tx_desc_base;
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/* Initialize all descriptors */
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for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
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cur_tx_desc++, i++) {
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cur_tx_desc->td0 = 0x00;
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cur_tx_desc->td1 = 0x00;
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cur_tx_desc->td2 = 0x00;
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}
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/* Mark the end of the descriptors */
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cur_tx_desc--;
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cur_tx_desc->td0 |= TD_TDLE;
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/* Point the controller to the tx descriptor list. Must use physical
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addresses */
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
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outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
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outl(0x01, TDFFR(port));/* Last discriptor bit */
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err:
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return ret;
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}
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static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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{
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int port = eth->port, i , ret = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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struct rx_desc_s *cur_rx_desc;
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u32 tmp_addr;
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u8 *rx_buf;
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/*
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* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
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*/
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port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
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sizeof(struct rx_desc_s) +
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RX_DESC_SIZE - 1);
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if (!port_info->rx_desc_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err;
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}
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tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
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~(RX_DESC_SIZE - 1));
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/* Make sure we use a P2 address (non-cacheable) */
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port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
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port_info->rx_desc_cur = port_info->rx_desc_base;
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/*
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* Allocate rx data buffers. They must be 32 bytes aligned and in
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* P2 area
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*/
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port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
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if (!port_info->rx_buf_malloc) {
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printf(SHETHER_NAME ": malloc failed\n");
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ret = -ENOMEM;
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goto err_buf_malloc;
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}
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tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
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~(32 - 1));
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port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
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/* Initialize all descriptors */
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for (cur_rx_desc = port_info->rx_desc_base,
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rx_buf = port_info->rx_buf_base, i = 0;
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i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
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cur_rx_desc->rd0 = RD_RACT;
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cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
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cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
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}
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/* Mark the end of the descriptors */
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cur_rx_desc--;
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cur_rx_desc->rd0 |= RD_RDLE;
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/* Point the controller to the rx descriptor list */
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
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outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
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outl(RDFFR_RDLF, RDFFR(port));
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return ret;
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err_buf_malloc:
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free(port_info->rx_desc_malloc);
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port_info->rx_desc_malloc = NULL;
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err:
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return ret;
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}
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static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (port_info->tx_desc_malloc) {
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free(port_info->tx_desc_malloc);
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port_info->tx_desc_malloc = NULL;
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}
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}
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static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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struct sh_eth_info *port_info = ð->port_info[port];
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if (port_info->rx_desc_malloc) {
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free(port_info->rx_desc_malloc);
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port_info->rx_desc_malloc = NULL;
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}
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if (port_info->rx_buf_malloc) {
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free(port_info->rx_buf_malloc);
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port_info->rx_buf_malloc = NULL;
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}
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}
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static int sh_eth_desc_init(struct sh_eth_dev *eth)
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{
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int ret = 0;
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ret = sh_eth_tx_desc_init(eth);
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if (ret)
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goto err_tx_init;
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ret = sh_eth_rx_desc_init(eth);
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if (ret)
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goto err_rx_init;
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return ret;
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err_rx_init:
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sh_eth_tx_desc_free(eth);
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err_tx_init:
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return ret;
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}
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static int sh_eth_phy_config(struct sh_eth_dev *eth)
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{
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int port = eth->port, timeout, ret = 0;
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struct sh_eth_info *port_info = ð->port_info[port];
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u32 val;
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/* Reset phy */
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sh_eth_mii_write_phy_reg
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(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
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timeout = 10;
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while (timeout--) {
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val = sh_eth_mii_read_phy_reg(port,
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port_info->phy_addr, PHY_CTRL);
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if (!(val & PHY_C_RESET))
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break;
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udelay(SH_ETH_PHY_DELAY);
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}
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if (timeout < 0) {
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printf(SHETHER_NAME ": phy reset timeout\n");
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ret = -EIO;
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goto err_tout;
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}
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/* Advertise 100/10 baseT full/half duplex */
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sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
|
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(PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
|
|
/* Autonegotiation, normal operation, full duplex, enable tx */
|
|
sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
|
|
(PHY_C_ANEGEN|PHY_C_RANEG));
|
|
/* Wait for autonegotiation to complete */
|
|
timeout = 100;
|
|
while (timeout--) {
|
|
val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
|
|
if (val & PHY_S_ANEGC)
|
|
break;
|
|
|
|
udelay(SH_ETH_PHY_DELAY);
|
|
}
|
|
|
|
if (timeout < 0) {
|
|
printf(SHETHER_NAME ": phy auto-negotiation failed\n");
|
|
ret = -ETIMEDOUT;
|
|
goto err_tout;
|
|
}
|
|
|
|
return ret;
|
|
|
|
err_tout:
|
|
return ret;
|
|
}
|
|
|
|
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
|
|
{
|
|
int port = eth->port, ret = 0;
|
|
u32 val, phy_status;
|
|
struct sh_eth_info *port_info = ð->port_info[port];
|
|
struct eth_device *dev = port_info->dev;
|
|
|
|
/* Configure e-dmac registers */
|
|
outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
|
|
outl(0, EESIPR(port));
|
|
outl(0, TRSCER(port));
|
|
outl(0, TFTR(port));
|
|
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
|
|
outl(RMCR_RST, RMCR(port));
|
|
outl(0, RPADIR(port));
|
|
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
|
|
|
|
/* Configure e-mac registers */
|
|
outl(0, ECSIPR(port));
|
|
|
|
/* Set Mac address */
|
|
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
|
|
dev->enetaddr[2] << 8 | dev->enetaddr[3];
|
|
outl(val, MAHR(port));
|
|
|
|
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
|
|
outl(val, MALR(port));
|
|
|
|
outl(RFLR_RFL_MIN, RFLR(port));
|
|
outl(0, PIPR(port));
|
|
outl(APR_AP, APR(port));
|
|
outl(MPR_MP, MPR(port));
|
|
outl(TPAUSER_TPAUSE, TPAUSER(port));
|
|
|
|
/* Configure phy */
|
|
ret = sh_eth_phy_config(eth);
|
|
if (ret) {
|
|
printf(SHETHER_NAME ": phy config timeout\n");
|
|
goto err_phy_cfg;
|
|
}
|
|
/* Read phy status to finish configuring the e-mac */
|
|
phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
|
|
|
|
/* Set the transfer speed */
|
|
if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
|
|
printf(SHETHER_NAME ": 100Base/");
|
|
outl(GECMR_100B, GECMR(port));
|
|
} else {
|
|
printf(SHETHER_NAME ": 10Base/");
|
|
outl(GECMR_10B, GECMR(port));
|
|
}
|
|
|
|
/* Check if full duplex mode is supported by the phy */
|
|
if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
|
|
printf("Full\n");
|
|
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
|
|
} else {
|
|
printf("Half\n");
|
|
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
|
|
}
|
|
|
|
return ret;
|
|
|
|
err_phy_cfg:
|
|
return ret;
|
|
}
|
|
|
|
static void sh_eth_start(struct sh_eth_dev *eth)
|
|
{
|
|
/*
|
|
* Enable the e-dmac receiver only. The transmitter will be enabled when
|
|
* we have something to transmit
|
|
*/
|
|
outl(EDRRR_R, EDRRR(eth->port));
|
|
}
|
|
|
|
static void sh_eth_stop(struct sh_eth_dev *eth)
|
|
{
|
|
outl(~EDRRR_R, EDRRR(eth->port));
|
|
}
|
|
|
|
int sh_eth_init(struct eth_device *dev, bd_t *bd)
|
|
{
|
|
int ret = 0;
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
|
|
ret = sh_eth_reset(eth);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = sh_eth_desc_init(eth);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = sh_eth_config(eth, bd);
|
|
if (ret)
|
|
goto err_config;
|
|
|
|
sh_eth_start(eth);
|
|
|
|
return ret;
|
|
|
|
err_config:
|
|
sh_eth_tx_desc_free(eth);
|
|
sh_eth_rx_desc_free(eth);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
void sh_eth_halt(struct eth_device *dev)
|
|
{
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
sh_eth_stop(eth);
|
|
}
|
|
|
|
int sh_eth_initialize(bd_t *bd)
|
|
{
|
|
int ret = 0;
|
|
struct sh_eth_dev *eth = NULL;
|
|
struct eth_device *dev = NULL;
|
|
|
|
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
|
|
if (!eth) {
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
|
if (!dev) {
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
memset(eth, 0, sizeof(struct sh_eth_dev));
|
|
|
|
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
|
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
|
|
|
dev->priv = (void *)eth;
|
|
dev->iobase = 0;
|
|
dev->init = sh_eth_init;
|
|
dev->halt = sh_eth_halt;
|
|
dev->send = sh_eth_send;
|
|
dev->recv = sh_eth_recv;
|
|
eth->port_info[eth->port].dev = dev;
|
|
|
|
sprintf(dev->name, SHETHER_NAME);
|
|
|
|
/* Register Device to EtherNet subsystem */
|
|
eth_register(dev);
|
|
|
|
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
|
|
puts("Please set MAC address\n");
|
|
|
|
return ret;
|
|
|
|
err:
|
|
if (dev)
|
|
free(dev);
|
|
|
|
if (eth)
|
|
free(eth);
|
|
|
|
printf(SHETHER_NAME ": Failed\n");
|
|
return ret;
|
|
}
|