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https://github.com/brain-hackers/u-boot-brain
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55c531984d
MPC837xE specs says that SerDes1 has: — Two lanes running x1 SGMII at 1.25 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. And for SerDes2: — Two lanes running x1 PCI Express at 2.5 Gbps; — One lane running x2 PCI Express at 2.5 Gbps; — Two lanes running x1 SATA at 1.5 or 3.0 Gbps. The spec also explicitly states that PEX options are not valid for the SD1. Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX, which is wrong to do. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
160 lines
4.2 KiB
C
160 lines
4.2 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* CREDITS: Kim Phillips contribute to LIBFDT code
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <spd_sdram.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../common/pq-mds-pib.h"
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#endif
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int board_early_init_f(void)
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{
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u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[0x9] &= ~0x04;
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/* Clear all of the interrupt of BCSR */
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bcsr[0xe] = 0xff;
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_PQ_MDS_PIB
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pib_init();
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#endif
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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#if (CONFIG_SYS_DDR_SIZE != 512)
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#warning Currenly any ddr size other than 512 is not supported
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#endif
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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udelay(1000);
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__("sync");
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udelay(1000);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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udelay(2000);
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return CONFIG_SYS_DDR_SIZE;
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}
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#endif /*!CONFIG_SYS_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC837xEMDS\n");
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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