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https://github.com/brain-hackers/u-boot-brain
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594d089c8a
LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef _ARCH_IRQ_H_
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#define _ARCH_IRQ_H_
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/**
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* Intel interrupt router configuration mechanism
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*
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* There are two known ways of Intel interrupt router configuration mechanism
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* so far. On most cases, the IRQ routing configuraiton is controlled by PCI
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* configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
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* On some newer platforms like BayTrail and Braswell, the IRQ routing is now
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* in the IBASE register block where IBASE is memory-mapped.
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*/
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enum pirq_config {
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PIRQ_VIA_PCI,
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PIRQ_VIA_IBASE
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};
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/**
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* Intel interrupt router control block
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*
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* Its members' value will be filled in based on device tree's input.
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*
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* @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
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* @link_base: link value base number
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* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
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* IRQ N is available to be routed
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* @lb_bdf: irq router's PCI bus/device/function number encoding
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* @ibase: IBASE register block base address
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* @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
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* @actl_addr: ACTL register offset
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*/
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struct irq_router {
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int config;
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u32 link_base;
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u16 irq_mask;
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u32 bdf;
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u32 ibase;
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bool actl_8bit;
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int actl_addr;
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};
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struct pirq_routing {
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int bdf;
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int pin;
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int pirq;
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};
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/**
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* pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
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*
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* @reg: PIRQ routing register offset from the base address
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* @base: PIRQ routing register block base address
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* @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
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*/
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static inline int pirq_reg_to_linkno(int reg, int base)
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{
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return reg - base;
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}
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/**
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* pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
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*
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* @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
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* @base: PIRQ routing register block base address
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* @return: PIRQ routing register offset from the base address
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*/
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static inline int pirq_linkno_to_reg(int linkno, int base)
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{
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return linkno + base;
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}
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#define PIRQ_BITMAP 0xdef8
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#endif /* _ARCH_IRQ_H_ */
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