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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 13:23:20 +09:00
![Peter Tyser](/assets/img/avatar_default.png)
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
394 lines
9.7 KiB
C
394 lines
9.7 KiB
C
/*
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* Copyright 2004, 2007, 2009-2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <spd_sdram.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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DECLARE_GLOBAL_DATA_PTR;
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void local_bus_init(void);
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void sdram_init(void);
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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/* PCI slot in USER bits CSR[6:7] by convention. */
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uint pci_slot = get_pci_slot ();
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uint cpu_board_rev = get_cpu_board_revision ();
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
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get_board_version (), pci_slot);
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printf ("CPU Board Revision %d.%d (0x%04x)\n",
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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/*
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* Hack TSEC 3 and 4 IO voltages.
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*/
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gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
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ecm->eedr = 0xffffffff; /* clear ecm errors */
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ecm->eeer = 0xffffffff; /* enable ecm errors */
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay(200);
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}
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#endif
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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/*
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* SDRAM Initialization
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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gur->lbiuiplldcr1 = 0x00078080;
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if (clkdiv == 16) {
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gur->lbiuiplldcr0 = 0x7c0f1bf0;
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} else if (clkdiv == 8) {
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gur->lbiuiplldcr0 = 0x6c0f1bf0;
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} else if (clkdiv == 4) {
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gur->lbiuiplldcr0 = 0x5c0f1bf0;
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}
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lbc->lcrr |= 0x00030000;
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asm("sync;isync;msync");
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
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uint idx;
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint cpu_board_rev;
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uint lsdmr_common;
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puts(" SDRAM: ");
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print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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asm("msync");
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/*
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* MPC8548 uses "new" 15-16 style addressing.
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*/
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cpu_board_rev = get_cpu_board_revision();
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lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
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lsdmr_common |= LSDMR_BSMA1516;
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/*
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* Issue PRECHARGE ALL command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue NORMAL OP command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
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/* For some reason the Tundra PCI bridge shows up on itself as a
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* different device. Work around that by refusing to configure it.
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*/
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void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
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static struct pci_config_table pci_mpc85xxcds_config_table[] = {
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{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
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{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
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{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
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mpc85xx_config_via_usbide, {0,0,0}},
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{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
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mpc85xx_config_via_usb, {0,0,0}},
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{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
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mpc85xx_config_via_usb2, {0,0,0}},
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{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
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mpc85xx_config_via_power, {0,0,0}},
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{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
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mpc85xx_config_via_ac97, {0,0,0}},
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{},
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};
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static struct pci_controller pci1_hose = {
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config_table: pci_mpc85xxcds_config_table};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCI2
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static struct pci_controller pci2_hose;
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[4];
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u32 devdisr, pordevsr, io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
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#ifdef CONFIG_PCI1
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pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
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pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pci1_hose, first_free_busno);
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#ifdef CONFIG_PCIX_CHECK
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if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
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/* PCI-X init */
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if (CONFIG_SYS_CLK_FREQ < 66000000)
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printf("PCI-X will only work at 66 MHz\n");
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reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
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}
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#endif
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} else {
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printf("PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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#ifdef CONFIG_PCI2
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{
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uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
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if (pci_dual) {
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printf("PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf("PCI2: disabled\n");
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}
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}
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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}
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int last_stage_init(void)
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{
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unsigned short temp;
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/* Change the resistors for the PHY */
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/* This is needed to get the RGMII working for the 1.3+
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* CDS cards */
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if (get_board_version() == 0x13) {
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miiphy_write(CONFIG_TSEC1_NAME,
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TSEC1_PHY_ADDR, 29, 18);
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miiphy_read(CONFIG_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, &temp);
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temp = (temp & 0xf03f);
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temp |= 2 << 9; /* 36 ohm */
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temp |= 2 << 6; /* 39 ohm */
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miiphy_write(CONFIG_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, temp);
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miiphy_write(CONFIG_TSEC1_NAME,
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TSEC1_PHY_ADDR, 29, 3);
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miiphy_write(CONFIG_TSEC1_NAME,
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TSEC1_PHY_ADDR, 30, 0x8000);
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}
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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FT_FSL_PCI_SETUP;
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}
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#endif
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