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https://github.com/brain-hackers/u-boot-brain
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6f6b7cfa89
This converts the following to Kconfig: CONFIG_CONS_INDEX We have existing entries for this option in a number of places, with different guards on them. They're also sometimes used for things not directly inside of the serial driver. First, introduce a new symbol to guard the use of CONFIG_CONS_INDEX, so that in the case where we don't need this for the serial driver, but for some other use, we can still do it. Next, consolidate all of these into the single entry in drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that we can imply a correct value here to make the defconfig side of this smaller. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Rework a lot of the logic here, such that I took authorship from Adam, but kept his S-o-B line] Signed-off-by: Tom Rini <trini@konsulko.com>
145 lines
4.7 KiB
C
145 lines
4.7 KiB
C
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* Configuration settings for the MX31ADS Freescale board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_MX31 1 /* This is a mx31 */
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#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_HARD_SPI 1
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#define CONFIG_DEFAULT_SPI_BUS 1
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#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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/* PMIC Controller */
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#define CONFIG_POWER
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#define CONFIG_POWER_SPI
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#define CONFIG_POWER_FSL
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#define CONFIG_FSL_PMIC_BUS 1
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"uboot_addr=0xa0000000\0" \
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"uboot=mx31ads/u-boot.bin\0" \
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"kernel=mx31ads/uImage\0" \
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"nfsroot=/opt/eldk/arm\0" \
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"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
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"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_nfs; " \
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"tftpboot ${loadaddr} ${kernel}; bootm\0" \
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"prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
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"protect off ${uboot_addr} 0xa003ffff; " \
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"erase ${uboot_addr} 0xa003ffff; " \
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"cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
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"setenv filesize; saveenv\0"
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#define CONFIG_CS8900
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#define CONFIG_CS8900_BASE 0xb4020300
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#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
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/*
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* The MX31ADS board seems to have a hardware "peculiarity" confirmed under
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* U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
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* controller inverted. The controller is capable of detecting and correcting
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* this, but it needs 4 network packets for that. Which means, at startup, you
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* will not receive answers to the first 4 packest, unless there have been some
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* broadcasts on the network, or your board is on a hub. Reducing the ARP
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* timeout from default 5 seconds to 200ms we speed up the initial TFTP
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* transfer, should the user wish one, significantly.
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*/
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#define CONFIG_ARP_TIMEOUT 200UL
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x10000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_GBL_DATA_OFFSET)
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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/*-----------------------------------------------------------------------
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* CFI FLASH driver setup
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*/
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#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
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#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
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/*
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* JFFS2 partitions
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*/
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#define CONFIG_JFFS2_DEV "nor0"
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#endif /* __CONFIG_H */
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