mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
553f09823c
CONFIG_SYS_INIT_RAM_END was a misnomer as it suggests this might be some end address; to make the meaning more clear we rename it into CONFIG_SYS_INIT_RAM_SIZE No other code changes are performed in this patch, only minor editing of white space (due to the changed length) and the comments was done, where noticed. Note that the code for the PATI and cmi_mpc5xx board configurations looks seriously broken. Last known maintainers on Cc: Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Denis Peter <d.peter@mpl.ch> Cc: Martin Winistoerfer <martinwinistoerfer@gmx.ch> Acked-by: Kumar Gala <galak@kernel.crashing.org>
267 lines
8.5 KiB
C
267 lines
8.5 KiB
C
/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _M5253DEMO_H
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#define _M5253DEMO_H
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#define CONFIG_MCF52x2 /* define processor family */
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#define CONFIG_M5253 /* define processor type */
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#define CONFIG_M5253DEMO /* define board type */
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#undef CONFIG_WATCHDOG /* disable watchdog */
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#define CONFIG_BOOTDELAY 5
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#ifdef CONFIG_MONITOR_IS_IN_RAM
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# define CONFIG_ENV_OFFSET 0x4000
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# define CONFIG_ENV_SECT_SIZE 0x1000
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# define CONFIG_ENV_IS_IN_FLASH 1
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#else
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# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
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# define CONFIG_ENV_SECT_SIZE 0x1000
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# define CONFIG_ENV_IS_IN_FLASH 1
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#endif
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_PING
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#ifdef CONFIG_CMD_IDE
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/* ATA */
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# define CONFIG_DOS_PARTITION
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# define CONFIG_MAC_PARTITION
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# define CONFIG_IDE_RESET 1
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# define CONFIG_IDE_PREINIT 1
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# define CONFIG_ATAPI
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# undef CONFIG_LBA48
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# define CONFIG_SYS_IDE_MAXBUS 1
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# define CONFIG_SYS_IDE_MAXDEVICE 2
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# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
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# define CONFIG_SYS_ATA_IDE0_OFFSET 0
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# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
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# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
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# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
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# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
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#endif
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#define CONFIG_NET_MULTI 1
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#define CONFIG_DRIVER_DM9000
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#ifdef CONFIG_DRIVER_DM9000
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# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
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# define DM9000_IO CONFIG_DM9000_BASE
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# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
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# undef CONFIG_DM9000_DEBUG
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# define CONFIG_OVERWRITE_ETHADDR_ONCE
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# define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
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"loadaddr=10000\0" \
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"u-boot=u-boot.bin\0" \
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"load=tftp ${loadaddr) ${u-boot}\0" \
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"upd=run load; run prog\0" \
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"prog=prot off 0xff800000 0xff82ffff;" \
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"era 0xff800000 0xff82ffff;" \
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"cp.b ${loadaddr} 0xff800000 ${filesize};" \
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"save\0" \
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""
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#endif
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#define CONFIG_HOSTNAME M5253DEMO
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/* I2C */
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#define CONFIG_FSL_I2C
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#define CONFIG_HARD_I2C /* I2C with hw support */
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#define CONFIG_SYS_I2C_SPEED 80000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define CONFIG_SYS_I2C_OFFSET 0x00000280
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#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
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#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
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#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
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#define CONFIG_SYS_I2C_PINMUX_SET (0)
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_MEMTEST_START 0x400
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#define CONFIG_SYS_MEMTEST_END 0x380000
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#define CONFIG_SYS_HZ 1000
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#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
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#define CONFIG_SYS_FAST_CLK
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#ifdef CONFIG_SYS_FAST_CLK
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# define CONFIG_SYS_PLLCR 0x1243E054
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# define CONFIG_SYS_CLK 140000000
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#else
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# define CONFIG_SYS_PLLCR 0x135a4140
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# define CONFIG_SYS_CLK 70000000
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
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#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
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/*
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
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#ifdef CONFIG_MONITOR_IS_IN_RAM
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# define CONFIG_SYS_MONITOR_BASE 0x20000
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#else
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# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_MONITOR_LEN 0x40000
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
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#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
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/* FLASH organization */
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#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
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#define FLASH_SST6401B 0x200
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#define SST_ID_xF6401B 0x236D236D
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#undef CONFIG_SYS_FLASH_CFI
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#ifdef CONFIG_SYS_FLASH_CFI
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/*
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* Unable to use CFI driver, due to incompatible sector erase command by SST.
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* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
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* 0x30 is block erase in SST
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*/
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# define CONFIG_FLASH_CFI_DRIVER 1
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# define CONFIG_SYS_FLASH_SIZE 0x800000
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# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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# define CONFIG_FLASH_CFI_LEGACY
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#else
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# define CONFIG_SYS_SST_SECT 2048
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# define CONFIG_SYS_SST_SECTSZ 0x1000
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# define CONFIG_SYS_FLASH_WRITE_TOUT 500
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#endif
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/* Cache Configuration */
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#define CONFIG_SYS_CACHELINE_SIZE 16
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#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 8)
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#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - 4)
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#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
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#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
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CF_ADDRMASK(8) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
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CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
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CF_ACR_EN | CF_ACR_SM_ALL)
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#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
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CF_CACR_DBWE)
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/* Port configuration */
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#define CONFIG_SYS_FECI2C 0xF0
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#define CONFIG_SYS_CS0_BASE 0xFF800000
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#define CONFIG_SYS_CS0_MASK 0x007F0021
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#define CONFIG_SYS_CS0_CTRL 0x00001D80
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#define CONFIG_SYS_CS1_BASE 0xE0000000
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#define CONFIG_SYS_CS1_MASK 0x00000001
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#define CONFIG_SYS_CS1_CTRL 0x00003DD8
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/*-----------------------------------------------------------------------
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* Port configuration
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*/
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#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
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#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
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#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
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#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
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#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
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#endif /* _M5253DEMO_H */
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