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https://github.com/brain-hackers/u-boot-brain
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fdff1f96a6
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
36 lines
709 B
C
36 lines
709 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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/*
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* cleanup_before_linux() is called just before we call linux
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* it prepares the processor for linux
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*
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* we disable interrupt and caches.
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*/
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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cache_flush();
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return 0;
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}
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/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */
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static const struct udevice_id riscv_virtio_soc_ids[] = {
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{ .compatible = "riscv-virtio-soc" },
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{ }
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};
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U_BOOT_DRIVER(riscv_virtio_soc) = {
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.name = "riscv_virtio_soc",
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.id = UCLASS_SIMPLE_BUS,
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.of_match = riscv_virtio_soc_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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