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https://github.com/brain-hackers/u-boot-brain
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dda00ae4ef
Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
22 lines
502 B
Plaintext
22 lines
502 B
Plaintext
config RISCV_NDS
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bool
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select ARCH_EARLY_INIT_R
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER
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imply ANDES_PLIC if RISCV_MMODE
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imply ANDES_PLMT if RISCV_MMODE
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help
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Run U-Boot on AndeStar V5 platforms and use some specific features
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which are provided by Andes Technology AndeStar V5 families.
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if RISCV_NDS
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config RISCV_NDS_CACHE
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bool "AndeStar V5 families specific cache support"
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depends on RISCV_MMODE
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help
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Provide Andes Technology AndeStar V5 families specific cache support.
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endif
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