mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
92 lines
1.9 KiB
C
92 lines
1.9 KiB
C
/*
|
|
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#ifndef __MX6_COMMON_H
|
|
#define __MX6_COMMON_H
|
|
|
|
#ifndef CONFIG_MX6UL
|
|
#ifndef CONFIG_SYS_L2CACHE_OFF
|
|
#define CONFIG_SYS_L2_PL310
|
|
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE
|
|
#endif
|
|
|
|
#define CONFIG_MP
|
|
#endif
|
|
#define CONFIG_BOARD_POSTCLK_INIT
|
|
#define CONFIG_MXC_GPT_HCLK
|
|
|
|
#define CONFIG_SYS_BOOTM_LEN 0x1000000
|
|
|
|
#include <linux/sizes.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/mach-imx/gpio.h>
|
|
|
|
#ifndef CONFIG_MX6
|
|
#define CONFIG_MX6
|
|
#endif
|
|
|
|
#define CONFIG_SYS_FSL_CLK
|
|
|
|
/* ATAGs */
|
|
#define CONFIG_CMDLINE_TAG
|
|
#define CONFIG_SETUP_MEMORY_TAGS
|
|
#define CONFIG_INITRD_TAG
|
|
#define CONFIG_REVISION_TAG
|
|
|
|
/* Boot options */
|
|
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \
|
|
defined(CONFIG_MX6UL) || defined(CONFIG_MX6SLL))
|
|
#define CONFIG_LOADADDR 0x82000000
|
|
#ifndef CONFIG_SYS_TEXT_BASE
|
|
#define CONFIG_SYS_TEXT_BASE 0x87800000
|
|
#endif
|
|
#else
|
|
#define CONFIG_LOADADDR 0x12000000
|
|
#ifndef CONFIG_SYS_TEXT_BASE
|
|
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
|
#endif
|
|
#endif
|
|
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
|
|
|
/* allow to overwrite serial and ethaddr */
|
|
#define CONFIG_ENV_OVERWRITE
|
|
#define CONFIG_CONS_INDEX 1
|
|
|
|
/* Filesystems and image support */
|
|
#define CONFIG_SUPPORT_RAW_INITRD
|
|
|
|
/* Miscellaneous configurable options */
|
|
#define CONFIG_SYS_LONGHELP
|
|
#define CONFIG_CMDLINE_EDITING
|
|
#define CONFIG_AUTO_COMPLETE
|
|
#define CONFIG_SYS_CBSIZE 512
|
|
#define CONFIG_SYS_MAXARGS 32
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
|
#ifndef CONFIG_SYS_DCACHE_OFF
|
|
#endif
|
|
|
|
/* GPIO */
|
|
#define CONFIG_MXC_GPIO
|
|
|
|
/* MMC */
|
|
#define CONFIG_BOUNCE_BUFFER
|
|
#define CONFIG_FSL_ESDHC
|
|
#define CONFIG_FSL_USDHC
|
|
|
|
/* Fuses */
|
|
#define CONFIG_MXC_OCOTP
|
|
|
|
/* Secure boot (HAB) support */
|
|
#ifdef CONFIG_SECURE_BOOT
|
|
#define CONFIG_CSF_SIZE 0x2000
|
|
#ifdef CONFIG_SPL_BUILD
|
|
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
|
|
#endif
|
|
#endif
|
|
|
|
#endif
|