mirror of
https://github.com/brain-hackers/u-boot-brain
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552a848e4f
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MXC_MXC_I2C_H__
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#define __ASM_ARCH_MXC_MXC_I2C_H__
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#include <asm-generic/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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struct i2c_pin_ctrl {
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iomux_v3_cfg_t i2c_mode;
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iomux_v3_cfg_t gpio_mode;
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unsigned char gp;
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unsigned char spare;
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};
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struct i2c_pads_info {
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struct i2c_pin_ctrl scl;
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struct i2c_pin_ctrl sda;
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};
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/*
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* Information about i2c controller
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* struct mxc_i2c_bus - information about the i2c[x] bus
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* @index: i2c bus index
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* @base: Address of I2C bus controller
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* @driver_data: Flags for different platforms, such as I2C_QUIRK_FLAG.
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* @speed: Speed of I2C bus
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* @pads_info: pinctrl info for this i2c bus, will be used when pinctrl is ok.
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* The following two is only to be compatible with non-DM part.
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* @idle_bus_fn: function to force bus idle
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* @idle_bus_data: parameter for idle_bus_fun
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* For DM:
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* bus: The device structure for i2c bus controller
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* scl-gpio: specify the gpio related to SCL pin
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* sda-gpio: specify the gpio related to SDA pin
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*/
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struct mxc_i2c_bus {
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/*
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* board file can use this index to locate which i2c_pads_info is for
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* i2c_idle_bus. When pinmux is implement, this entry can be
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* discarded. Here we do not use dev->seq, because we do not want to
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* export device to board file.
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*/
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int index;
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ulong base;
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ulong driver_data;
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int speed;
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struct i2c_pads_info *pads_info;
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#ifndef CONFIG_DM_I2C
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int (*idle_bus_fn)(void *p);
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void *idle_bus_data;
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#else
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struct udevice *bus;
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/* Use gpio to force bus idle when bus state is abnormal */
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struct gpio_desc scl_gpio;
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struct gpio_desc sda_gpio;
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#endif
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};
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#if defined(CONFIG_MX6QDL)
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#define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
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struct i2c_pads_info mx6q_##name = { \
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.scl = { \
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.i2c_mode = MX6Q_##scl_i2c, \
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.gpio_mode = MX6Q_##scl_gpio, \
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.gp = scl_gp, \
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}, \
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.sda = { \
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.i2c_mode = MX6Q_##sda_i2c, \
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.gpio_mode = MX6Q_##sda_gpio, \
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.gp = sda_gp, \
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} \
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}; \
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struct i2c_pads_info mx6s_##name = { \
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.scl = { \
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.i2c_mode = MX6DL_##scl_i2c, \
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.gpio_mode = MX6DL_##scl_gpio, \
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.gp = scl_gp, \
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}, \
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.sda = { \
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.i2c_mode = MX6DL_##sda_i2c, \
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.gpio_mode = MX6DL_##sda_gpio, \
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.gp = sda_gp, \
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} \
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};
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#define I2C_PADS_INFO(name) \
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(is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) ? \
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&mx6q_##name : &mx6s_##name
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#endif
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int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
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struct i2c_pads_info *p);
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void bus_i2c_init(int index, int speed, int slave_addr,
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int (*idle_bus_fn)(void *p), void *p);
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int force_idle_bus(void *priv);
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int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus);
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#endif
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