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552a848e4f
u-boot-brain/arch/arm/include/asm/arch-mxs/sys_proto.h
Stefano Babic 552a848e4f imx: reorganize IMX code as other SOCs 
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00

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/*
* Freescale i.MX23/i.MX28 specific functions
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __MXS_SYS_PROTO_H__
#define __MXS_SYS_PROTO_H__
#include <asm/mach-imx/sys_proto.h>
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
#elif defined(CONFIG_MX28)
#include <asm/arch/iomux-mx28.h>
#endif
void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
#endif
struct mxs_pair {
uint8_t boot_pads;
uint8_t boot_mask;
const char *mode;
};
static const struct mxs_pair mxs_boot_modes[] = {
#if defined(CONFIG_MX23)
{ 0x00, 0x0f, "USB" },
{ 0x01, 0x1f, "I2C, master" },
{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
{ 0x04, 0x1f, "NAND" },
{ 0x06, 0x1f, "JTAG" },
{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
{ 0x09, 0x1f, "SSP SD/MMC #0" },
{ 0x0a, 0x1f, "SSP SD/MMC #1" },
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
#elif defined(CONFIG_MX28)
{ 0x00, 0x0f, "USB #0" },
{ 0x01, 0x1f, "I2C #0, master, 3V3" },
{ 0x11, 0x1f, "I2C #0, master, 1V8" },
{ 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
{ 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
{ 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
{ 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
{ 0x04, 0x1f, "NAND, 3V3" },
{ 0x14, 0x1f, "NAND, 1V8" },
{ 0x06, 0x1f, "JTAG" },
{ 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
{ 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
{ 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
{ 0x19, 0x1f, "SSP SD/MMC #0, 1V8" },
{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
#endif
};
#define MXS_BM_USB 0x00
#define MXS_BM_I2C_MASTER_3V3 0x01
#define MXS_BM_I2C_MASTER_1V8 0x11
#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02
#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12
#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03
#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13
#define MXS_BM_NAND_3V3 0x04
#define MXS_BM_NAND_1V8 0x14
#define MXS_BM_JTAG 0x06
#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08
#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18
#define MXS_BM_SDMMC0_3V3 0x09
#define MXS_BM_SDMMC0_1V8 0x19
#define MXS_BM_SDMMC1_3V3 0x0a
#define MXS_BM_SDMMC1_1V8 0x1a
struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_t mem_dram_size;
};
int mxs_dram_init(void);
#endif /* __SYS_PROTO_H__ */
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