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https://github.com/brain-hackers/u-boot-brain
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![Lucas Stach](/assets/img/avatar_default.png)
usb_hub_descriptor has to be packed as it's used for communication with the device. Member wHubCharacteristics violates the natural alignment rules. Use explicit unaligned access functions for this member. Fixes ARMv7 traping while using USB. v2: fix typo found by Thomas Langer v3: rebased on top of u-boot-usb/master Signed-off-by: Lucas Stach <dev@lynxeye.de>
957 lines
27 KiB
C
957 lines
27 KiB
C
/*-
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* Copyright (c) 2007-2008, Juniper Networks, Inc.
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* Copyright (c) 2008, Excito Elektronik i Skåne AB
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* Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <asm/unaligned.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <watchdog.h>
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#include "ehci.h"
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int rootdev;
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struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
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volatile struct ehci_hcor *hcor;
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static uint16_t portreset;
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DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
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#define ALIGN_END_ADDR(type, ptr, size) \
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((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
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static struct descriptor {
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struct usb_hub_descriptor hub;
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struct usb_device_descriptor device;
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struct usb_linux_config_descriptor config;
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struct usb_linux_interface_descriptor interface;
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struct usb_endpoint_descriptor endpoint;
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} __attribute__ ((packed)) descriptor = {
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{
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0x8, /* bDescLength */
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0x29, /* bDescriptorType: hub descriptor */
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2, /* bNrPorts -- runtime modified */
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0, /* wHubCharacteristics */
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10, /* bPwrOn2PwrGood */
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0, /* bHubCntrCurrent */
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{}, /* Device removable */
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{} /* at most 7 ports! XXX */
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},
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{
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0x12, /* bLength */
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1, /* bDescriptorType: UDESC_DEVICE */
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cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
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9, /* bDeviceClass: UDCLASS_HUB */
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0, /* bDeviceSubClass: UDSUBCLASS_HUB */
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1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
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64, /* bMaxPacketSize: 64 bytes */
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0x0000, /* idVendor */
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0x0000, /* idProduct */
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cpu_to_le16(0x0100), /* bcdDevice */
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1, /* iManufacturer */
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2, /* iProduct */
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0, /* iSerialNumber */
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1 /* bNumConfigurations: 1 */
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},
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{
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0x9,
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2, /* bDescriptorType: UDESC_CONFIG */
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cpu_to_le16(0x19),
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1, /* bNumInterface */
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1, /* bConfigurationValue */
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0, /* iConfiguration */
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0x40, /* bmAttributes: UC_SELF_POWER */
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0 /* bMaxPower */
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},
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{
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0x9, /* bLength */
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4, /* bDescriptorType: UDESC_INTERFACE */
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0, /* bInterfaceNumber */
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0, /* bAlternateSetting */
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1, /* bNumEndpoints */
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9, /* bInterfaceClass: UICLASS_HUB */
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0, /* bInterfaceSubClass: UISUBCLASS_HUB */
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0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
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0 /* iInterface */
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},
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{
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0x7, /* bLength */
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5, /* bDescriptorType: UDESC_ENDPOINT */
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0x81, /* bEndpointAddress:
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* UE_DIR_IN | EHCI_INTR_ENDPT
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*/
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3, /* bmAttributes: UE_INTERRUPT */
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8, /* wMaxPacketSize */
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255 /* bInterval */
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},
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};
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#if defined(CONFIG_EHCI_IS_TDI)
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#define ehci_is_TDI() (1)
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#else
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#define ehci_is_TDI() (0)
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#endif
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void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
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{
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mdelay(50);
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}
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void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
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__attribute__((weak, alias("__ehci_powerup_fixup")));
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static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
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{
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uint32_t result;
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do {
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result = ehci_readl(ptr);
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udelay(5);
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if (result == ~(uint32_t)0)
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return -1;
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result &= mask;
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if (result == done)
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return 0;
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usec--;
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} while (usec > 0);
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return -1;
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}
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static int ehci_reset(void)
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{
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uint32_t cmd;
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uint32_t tmp;
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uint32_t *reg_ptr;
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int ret = 0;
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cmd = ehci_readl(&hcor->or_usbcmd);
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cmd = (cmd & ~CMD_RUN) | CMD_RESET;
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ehci_writel(&hcor->or_usbcmd, cmd);
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ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
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if (ret < 0) {
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printf("EHCI fail to reset\n");
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goto out;
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}
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if (ehci_is_TDI()) {
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reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
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tmp = ehci_readl(reg_ptr);
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tmp |= USBMODE_CM_HC;
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#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
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tmp |= USBMODE_BE;
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#endif
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ehci_writel(reg_ptr, tmp);
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}
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#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
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cmd = ehci_readl(&hcor->or_txfilltuning);
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cmd &= ~TXFIFO_THRESH_MASK;
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cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
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ehci_writel(&hcor->or_txfilltuning, cmd);
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#endif
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out:
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return ret;
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}
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static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
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{
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uint32_t delta, next;
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uint32_t addr = (uint32_t)buf;
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int idx;
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if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
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debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
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flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
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idx = 0;
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while (idx < QT_BUFFER_CNT) {
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td->qt_buffer[idx] = cpu_to_hc32(addr);
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td->qt_buffer_hi[idx] = 0;
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next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
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delta = next - addr;
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if (delta >= sz)
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break;
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sz -= delta;
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addr = next;
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idx++;
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}
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if (idx == QT_BUFFER_CNT) {
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printf("out of buffer pointers (%u bytes left)\n", sz);
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return -1;
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}
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return 0;
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}
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static int
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ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
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int length, struct devrequest *req)
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{
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ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
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struct qTD *qtd;
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int qtd_count = 0;
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int qtd_counter = 0;
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volatile struct qTD *vtd;
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unsigned long ts;
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uint32_t *tdp;
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uint32_t endpt, maxpacket, token, usbsts;
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uint32_t c, toggle;
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uint32_t cmd;
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int timeout;
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int ret = 0;
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debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
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buffer, length, req);
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if (req != NULL)
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debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
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req->request, req->request,
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req->requesttype, req->requesttype,
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le16_to_cpu(req->value), le16_to_cpu(req->value),
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le16_to_cpu(req->index));
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#define PKT_ALIGN 512
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/*
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* The USB transfer is split into qTD transfers. Eeach qTD transfer is
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* described by a transfer descriptor (the qTD). The qTDs form a linked
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* list with a queue head (QH).
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*
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* Each qTD transfer starts with a new USB packet, i.e. a packet cannot
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* have its beginning in a qTD transfer and its end in the following
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* one, so the qTD transfer lengths have to be chosen accordingly.
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*
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* Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
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* single pages. The first data buffer can start at any offset within a
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* page (not considering the cache-line alignment issues), while the
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* following buffers must be page-aligned. There is no alignment
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* constraint on the size of a qTD transfer.
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*/
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if (req != NULL)
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/* 1 qTD will be needed for SETUP, and 1 for ACK. */
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qtd_count += 1 + 1;
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if (length > 0 || req == NULL) {
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/*
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* Determine the qTD transfer size that will be used for the
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* data payload (not considering the first qTD transfer, which
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* may be longer or shorter, and the final one, which may be
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* shorter).
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*
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* In order to keep each packet within a qTD transfer, the qTD
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* transfer size is aligned to PKT_ALIGN, which is a multiple of
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* wMaxPacketSize (except in some cases for interrupt transfers,
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* see comment in submit_int_msg()).
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*
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* By default, i.e. if the input buffer is aligned to PKT_ALIGN,
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* QT_BUFFER_CNT full pages will be used.
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*/
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int xfr_sz = QT_BUFFER_CNT;
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/*
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* However, if the input buffer is not aligned to PKT_ALIGN, the
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* qTD transfer size will be one page shorter, and the first qTD
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* data buffer of each transfer will be page-unaligned.
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*/
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if ((uint32_t)buffer & (PKT_ALIGN - 1))
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xfr_sz--;
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/* Convert the qTD transfer size to bytes. */
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xfr_sz *= EHCI_PAGE_SIZE;
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/*
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* Approximate by excess the number of qTDs that will be
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* required for the data payload. The exact formula is way more
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* complicated and saves at most 2 qTDs, i.e. a total of 128
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* bytes.
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*/
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qtd_count += 2 + length / xfr_sz;
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}
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/*
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* Threshold value based on the worst-case total size of the allocated qTDs for
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* a mass-storage transfer of 65535 blocks of 512 bytes.
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*/
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#if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
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#warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
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#endif
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qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
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if (qtd == NULL) {
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printf("unable to allocate TDs\n");
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return -1;
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}
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memset(qh, 0, sizeof(struct QH));
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memset(qtd, 0, qtd_count * sizeof(*qtd));
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toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
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/*
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* Setup QH (3.6 in ehci-r10.pdf)
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*
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* qh_link ................. 03-00 H
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* qh_endpt1 ............... 07-04 H
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* qh_endpt2 ............... 0B-08 H
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* - qh_curtd
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* qh_overlay.qt_next ...... 13-10 H
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* - qh_overlay.qt_altnext
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*/
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qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
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c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
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maxpacket = usb_maxpacket(dev, pipe);
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endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
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QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
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QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
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QH_ENDPT1_EPS(usb_pipespeed(pipe)) |
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QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
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QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
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qh->qh_endpt1 = cpu_to_hc32(endpt);
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endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_PORTNUM(dev->portnr) |
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QH_ENDPT2_HUBADDR(dev->parent->devnum) |
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QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
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qh->qh_endpt2 = cpu_to_hc32(endpt);
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qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
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tdp = &qh->qh_overlay.qt_next;
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if (req != NULL) {
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/*
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* Setup request qTD (3.5 in ehci-r10.pdf)
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*
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* qt_next ................ 03-00 H
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* qt_altnext ............. 07-04 H
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* qt_token ............... 0B-08 H
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*
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* [ buffer, buffer_hi ] loaded with "req".
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*/
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qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
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qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
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token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
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QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
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QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
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QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
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qtd[qtd_counter].qt_token = cpu_to_hc32(token);
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if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
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printf("unable to construct SETUP TD\n");
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goto fail;
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}
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/* Update previous qTD! */
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*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
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tdp = &qtd[qtd_counter++].qt_next;
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toggle = 1;
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}
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if (length > 0 || req == NULL) {
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uint8_t *buf_ptr = buffer;
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int left_length = length;
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do {
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/*
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* Determine the size of this qTD transfer. By default,
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* QT_BUFFER_CNT full pages can be used.
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*/
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int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
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/*
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* However, if the input buffer is not page-aligned, the
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* portion of the first page before the buffer start
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* offset within that page is unusable.
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*/
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xfr_bytes -= (uint32_t)buf_ptr & (EHCI_PAGE_SIZE - 1);
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/*
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* In order to keep each packet within a qTD transfer,
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* align the qTD transfer size to PKT_ALIGN.
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*/
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xfr_bytes &= ~(PKT_ALIGN - 1);
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/*
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* This transfer may be shorter than the available qTD
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* transfer size that has just been computed.
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*/
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xfr_bytes = min(xfr_bytes, left_length);
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/*
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* Setup request qTD (3.5 in ehci-r10.pdf)
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*
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* qt_next ................ 03-00 H
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* qt_altnext ............. 07-04 H
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* qt_token ............... 0B-08 H
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*
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* [ buffer, buffer_hi ] loaded with "buffer".
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*/
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qtd[qtd_counter].qt_next =
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cpu_to_hc32(QT_NEXT_TERMINATE);
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qtd[qtd_counter].qt_altnext =
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cpu_to_hc32(QT_NEXT_TERMINATE);
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token = QT_TOKEN_DT(toggle) |
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QT_TOKEN_TOTALBYTES(xfr_bytes) |
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QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
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QT_TOKEN_CERR(3) |
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QT_TOKEN_PID(usb_pipein(pipe) ?
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QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
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QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
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qtd[qtd_counter].qt_token = cpu_to_hc32(token);
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if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
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xfr_bytes)) {
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printf("unable to construct DATA TD\n");
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goto fail;
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}
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/* Update previous qTD! */
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*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
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tdp = &qtd[qtd_counter++].qt_next;
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/*
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* Data toggle has to be adjusted since the qTD transfer
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* size is not always an even multiple of
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* wMaxPacketSize.
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*/
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if ((xfr_bytes / maxpacket) & 1)
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toggle ^= 1;
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buf_ptr += xfr_bytes;
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left_length -= xfr_bytes;
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} while (left_length > 0);
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}
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if (req != NULL) {
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/*
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* Setup request qTD (3.5 in ehci-r10.pdf)
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*
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* qt_next ................ 03-00 H
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* qt_altnext ............. 07-04 H
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* qt_token ............... 0B-08 H
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*/
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qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
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qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
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token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
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QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
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QT_TOKEN_PID(usb_pipein(pipe) ?
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QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
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QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
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qtd[qtd_counter].qt_token = cpu_to_hc32(token);
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/* Update previous qTD! */
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*tdp = cpu_to_hc32((uint32_t)&qtd[qtd_counter]);
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tdp = &qtd[qtd_counter++].qt_next;
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}
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|
|
qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
|
|
|
|
/* Flush dcache */
|
|
flush_dcache_range((uint32_t)qh_list,
|
|
ALIGN_END_ADDR(struct QH, qh_list, 1));
|
|
flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
|
|
flush_dcache_range((uint32_t)qtd,
|
|
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
|
|
|
|
/* Set async. queue head pointer. */
|
|
ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
|
|
|
|
usbsts = ehci_readl(&hcor->or_usbsts);
|
|
ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
|
|
|
|
/* Enable async. schedule. */
|
|
cmd = ehci_readl(&hcor->or_usbcmd);
|
|
cmd |= CMD_ASE;
|
|
ehci_writel(&hcor->or_usbcmd, cmd);
|
|
|
|
ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
|
|
100 * 1000);
|
|
if (ret < 0) {
|
|
printf("EHCI fail timeout STS_ASS set\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Wait for TDs to be processed. */
|
|
ts = get_timer(0);
|
|
vtd = &qtd[qtd_counter - 1];
|
|
timeout = USB_TIMEOUT_MS(pipe);
|
|
do {
|
|
/* Invalidate dcache */
|
|
invalidate_dcache_range((uint32_t)qh_list,
|
|
ALIGN_END_ADDR(struct QH, qh_list, 1));
|
|
invalidate_dcache_range((uint32_t)qh,
|
|
ALIGN_END_ADDR(struct QH, qh, 1));
|
|
invalidate_dcache_range((uint32_t)qtd,
|
|
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
|
|
|
|
token = hc32_to_cpu(vtd->qt_token);
|
|
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
|
|
break;
|
|
WATCHDOG_RESET();
|
|
} while (get_timer(ts) < timeout);
|
|
|
|
/*
|
|
* Invalidate the memory area occupied by buffer
|
|
* Don't try to fix the buffer alignment, if it isn't properly
|
|
* aligned it's upper layer's fault so let invalidate_dcache_range()
|
|
* vow about it. But we have to fix the length as it's actual
|
|
* transfer length and can be unaligned. This is potentially
|
|
* dangerous operation, it's responsibility of the calling
|
|
* code to make sure enough space is reserved.
|
|
*/
|
|
invalidate_dcache_range((uint32_t)buffer,
|
|
ALIGN((uint32_t)buffer + length, ARCH_DMA_MINALIGN));
|
|
|
|
/* Check that the TD processing happened */
|
|
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
|
|
printf("EHCI timed out on TD - token=%#x\n", token);
|
|
|
|
/* Disable async schedule. */
|
|
cmd = ehci_readl(&hcor->or_usbcmd);
|
|
cmd &= ~CMD_ASE;
|
|
ehci_writel(&hcor->or_usbcmd, cmd);
|
|
|
|
ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
|
|
100 * 1000);
|
|
if (ret < 0) {
|
|
printf("EHCI fail timeout STS_ASS reset\n");
|
|
goto fail;
|
|
}
|
|
|
|
token = hc32_to_cpu(qh->qh_overlay.qt_token);
|
|
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
|
|
debug("TOKEN=%#x\n", token);
|
|
switch (QT_TOKEN_GET_STATUS(token) &
|
|
~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
|
|
case 0:
|
|
toggle = QT_TOKEN_GET_DT(token);
|
|
usb_settoggle(dev, usb_pipeendpoint(pipe),
|
|
usb_pipeout(pipe), toggle);
|
|
dev->status = 0;
|
|
break;
|
|
case QT_TOKEN_STATUS_HALTED:
|
|
dev->status = USB_ST_STALLED;
|
|
break;
|
|
case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
|
|
case QT_TOKEN_STATUS_DATBUFERR:
|
|
dev->status = USB_ST_BUF_ERR;
|
|
break;
|
|
case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
|
|
case QT_TOKEN_STATUS_BABBLEDET:
|
|
dev->status = USB_ST_BABBLE_DET;
|
|
break;
|
|
default:
|
|
dev->status = USB_ST_CRC_ERR;
|
|
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
|
|
dev->status |= USB_ST_STALLED;
|
|
break;
|
|
}
|
|
dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
|
|
} else {
|
|
dev->act_len = 0;
|
|
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
|
|
dev->devnum, ehci_readl(&hcor->or_usbsts),
|
|
ehci_readl(&hcor->or_portsc[0]),
|
|
ehci_readl(&hcor->or_portsc[1]));
|
|
}
|
|
|
|
free(qtd);
|
|
return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
|
|
|
|
fail:
|
|
free(qtd);
|
|
return -1;
|
|
}
|
|
|
|
static inline int min3(int a, int b, int c)
|
|
{
|
|
|
|
if (b < a)
|
|
a = b;
|
|
if (c < a)
|
|
a = c;
|
|
return a;
|
|
}
|
|
|
|
int
|
|
ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
|
|
int length, struct devrequest *req)
|
|
{
|
|
uint8_t tmpbuf[4];
|
|
u16 typeReq;
|
|
void *srcptr = NULL;
|
|
int len, srclen;
|
|
uint32_t reg;
|
|
uint32_t *status_reg;
|
|
|
|
if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
|
|
printf("The request port(%d) is not configured\n",
|
|
le16_to_cpu(req->index) - 1);
|
|
return -1;
|
|
}
|
|
status_reg = (uint32_t *)&hcor->or_portsc[
|
|
le16_to_cpu(req->index) - 1];
|
|
srclen = 0;
|
|
|
|
debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
|
|
req->request, req->request,
|
|
req->requesttype, req->requesttype,
|
|
le16_to_cpu(req->value), le16_to_cpu(req->index));
|
|
|
|
typeReq = req->request | req->requesttype << 8;
|
|
|
|
switch (typeReq) {
|
|
case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
|
|
switch (le16_to_cpu(req->value) >> 8) {
|
|
case USB_DT_DEVICE:
|
|
debug("USB_DT_DEVICE request\n");
|
|
srcptr = &descriptor.device;
|
|
srclen = descriptor.device.bLength;
|
|
break;
|
|
case USB_DT_CONFIG:
|
|
debug("USB_DT_CONFIG config\n");
|
|
srcptr = &descriptor.config;
|
|
srclen = descriptor.config.bLength +
|
|
descriptor.interface.bLength +
|
|
descriptor.endpoint.bLength;
|
|
break;
|
|
case USB_DT_STRING:
|
|
debug("USB_DT_STRING config\n");
|
|
switch (le16_to_cpu(req->value) & 0xff) {
|
|
case 0: /* Language */
|
|
srcptr = "\4\3\1\0";
|
|
srclen = 4;
|
|
break;
|
|
case 1: /* Vendor */
|
|
srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
|
|
srclen = 14;
|
|
break;
|
|
case 2: /* Product */
|
|
srcptr = "\52\3E\0H\0C\0I\0 "
|
|
"\0H\0o\0s\0t\0 "
|
|
"\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
|
|
srclen = 42;
|
|
break;
|
|
default:
|
|
debug("unknown value DT_STRING %x\n",
|
|
le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
default:
|
|
debug("unknown value %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
|
|
switch (le16_to_cpu(req->value) >> 8) {
|
|
case USB_DT_HUB:
|
|
debug("USB_DT_HUB config\n");
|
|
srcptr = &descriptor.hub;
|
|
srclen = descriptor.hub.bLength;
|
|
break;
|
|
default:
|
|
debug("unknown value %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
break;
|
|
case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
|
|
debug("USB_REQ_SET_ADDRESS\n");
|
|
rootdev = le16_to_cpu(req->value);
|
|
break;
|
|
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
|
|
debug("USB_REQ_SET_CONFIGURATION\n");
|
|
/* Nothing to do */
|
|
break;
|
|
case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
|
|
tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
|
|
tmpbuf[1] = 0;
|
|
srcptr = tmpbuf;
|
|
srclen = 2;
|
|
break;
|
|
case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
|
|
memset(tmpbuf, 0, 4);
|
|
reg = ehci_readl(status_reg);
|
|
if (reg & EHCI_PS_CS)
|
|
tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
|
|
if (reg & EHCI_PS_PE)
|
|
tmpbuf[0] |= USB_PORT_STAT_ENABLE;
|
|
if (reg & EHCI_PS_SUSP)
|
|
tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
|
|
if (reg & EHCI_PS_OCA)
|
|
tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
|
|
if (reg & EHCI_PS_PR)
|
|
tmpbuf[0] |= USB_PORT_STAT_RESET;
|
|
if (reg & EHCI_PS_PP)
|
|
tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
|
|
|
|
if (ehci_is_TDI()) {
|
|
switch (PORTSC_PSPD(reg)) {
|
|
case PORTSC_PSPD_FS:
|
|
break;
|
|
case PORTSC_PSPD_LS:
|
|
tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
|
|
break;
|
|
case PORTSC_PSPD_HS:
|
|
default:
|
|
tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
|
|
break;
|
|
}
|
|
} else {
|
|
tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
|
|
}
|
|
|
|
if (reg & EHCI_PS_CSC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
|
|
if (reg & EHCI_PS_PEC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
|
|
if (reg & EHCI_PS_OCC)
|
|
tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
|
|
if (portreset & (1 << le16_to_cpu(req->index)))
|
|
tmpbuf[2] |= USB_PORT_STAT_C_RESET;
|
|
|
|
srcptr = tmpbuf;
|
|
srclen = 4;
|
|
break;
|
|
case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
|
|
reg = ehci_readl(status_reg);
|
|
reg &= ~EHCI_PS_CLEAR;
|
|
switch (le16_to_cpu(req->value)) {
|
|
case USB_PORT_FEAT_ENABLE:
|
|
reg |= EHCI_PS_PE;
|
|
ehci_writel(status_reg, reg);
|
|
break;
|
|
case USB_PORT_FEAT_POWER:
|
|
if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
|
|
reg |= EHCI_PS_PP;
|
|
ehci_writel(status_reg, reg);
|
|
}
|
|
break;
|
|
case USB_PORT_FEAT_RESET:
|
|
if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
|
|
!ehci_is_TDI() &&
|
|
EHCI_PS_IS_LOWSPEED(reg)) {
|
|
/* Low speed device, give up ownership. */
|
|
debug("port %d low speed --> companion\n",
|
|
req->index - 1);
|
|
reg |= EHCI_PS_PO;
|
|
ehci_writel(status_reg, reg);
|
|
break;
|
|
} else {
|
|
int ret;
|
|
|
|
reg |= EHCI_PS_PR;
|
|
reg &= ~EHCI_PS_PE;
|
|
ehci_writel(status_reg, reg);
|
|
/*
|
|
* caller must wait, then call GetPortStatus
|
|
* usb 2.0 specification say 50 ms resets on
|
|
* root
|
|
*/
|
|
ehci_powerup_fixup(status_reg, ®);
|
|
|
|
ehci_writel(status_reg, reg & ~EHCI_PS_PR);
|
|
/*
|
|
* A host controller must terminate the reset
|
|
* and stabilize the state of the port within
|
|
* 2 milliseconds
|
|
*/
|
|
ret = handshake(status_reg, EHCI_PS_PR, 0,
|
|
2 * 1000);
|
|
if (!ret)
|
|
portreset |=
|
|
1 << le16_to_cpu(req->index);
|
|
else
|
|
printf("port(%d) reset error\n",
|
|
le16_to_cpu(req->index) - 1);
|
|
}
|
|
break;
|
|
default:
|
|
debug("unknown feature %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
/* unblock posted writes */
|
|
(void) ehci_readl(&hcor->or_usbcmd);
|
|
break;
|
|
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
|
|
reg = ehci_readl(status_reg);
|
|
switch (le16_to_cpu(req->value)) {
|
|
case USB_PORT_FEAT_ENABLE:
|
|
reg &= ~EHCI_PS_PE;
|
|
break;
|
|
case USB_PORT_FEAT_C_ENABLE:
|
|
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
|
|
break;
|
|
case USB_PORT_FEAT_POWER:
|
|
if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
|
|
reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
|
|
case USB_PORT_FEAT_C_CONNECTION:
|
|
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
|
|
break;
|
|
case USB_PORT_FEAT_OVER_CURRENT:
|
|
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
|
|
break;
|
|
case USB_PORT_FEAT_C_RESET:
|
|
portreset &= ~(1 << le16_to_cpu(req->index));
|
|
break;
|
|
default:
|
|
debug("unknown feature %x\n", le16_to_cpu(req->value));
|
|
goto unknown;
|
|
}
|
|
ehci_writel(status_reg, reg);
|
|
/* unblock posted write */
|
|
(void) ehci_readl(&hcor->or_usbcmd);
|
|
break;
|
|
default:
|
|
debug("Unknown request\n");
|
|
goto unknown;
|
|
}
|
|
|
|
mdelay(1);
|
|
len = min3(srclen, le16_to_cpu(req->length), length);
|
|
if (srcptr != NULL && len > 0)
|
|
memcpy(buffer, srcptr, len);
|
|
else
|
|
debug("Len is 0\n");
|
|
|
|
dev->act_len = len;
|
|
dev->status = 0;
|
|
return 0;
|
|
|
|
unknown:
|
|
debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
|
|
req->requesttype, req->request, le16_to_cpu(req->value),
|
|
le16_to_cpu(req->index), le16_to_cpu(req->length));
|
|
|
|
dev->act_len = 0;
|
|
dev->status = USB_ST_STALLED;
|
|
return -1;
|
|
}
|
|
|
|
int usb_lowlevel_stop(void)
|
|
{
|
|
return ehci_hcd_stop();
|
|
}
|
|
|
|
int usb_lowlevel_init(void)
|
|
{
|
|
uint32_t reg;
|
|
uint32_t cmd;
|
|
|
|
if (ehci_hcd_init())
|
|
return -1;
|
|
|
|
/* EHCI spec section 4.1 */
|
|
if (ehci_reset())
|
|
return -1;
|
|
|
|
#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
|
|
if (ehci_hcd_init())
|
|
return -1;
|
|
#endif
|
|
|
|
/* Set head of reclaim list */
|
|
memset(qh_list, 0, sizeof(*qh_list));
|
|
qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
|
|
qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
|
|
QH_ENDPT1_EPS(USB_SPEED_HIGH));
|
|
qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
|
|
qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
|
|
qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
|
|
qh_list->qh_overlay.qt_token =
|
|
cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
|
|
|
|
reg = ehci_readl(&hccr->cr_hcsparams);
|
|
descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
|
|
printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
|
|
/* Port Indicators */
|
|
if (HCS_INDICATOR(reg))
|
|
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
|
|
| 0x80, &descriptor.hub.wHubCharacteristics);
|
|
/* Port Power Control */
|
|
if (HCS_PPC(reg))
|
|
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
|
|
| 0x01, &descriptor.hub.wHubCharacteristics);
|
|
|
|
/* Start the host controller. */
|
|
cmd = ehci_readl(&hcor->or_usbcmd);
|
|
/*
|
|
* Philips, Intel, and maybe others need CMD_RUN before the
|
|
* root hub will detect new devices (why?); NEC doesn't
|
|
*/
|
|
cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
|
|
cmd |= CMD_RUN;
|
|
ehci_writel(&hcor->or_usbcmd, cmd);
|
|
|
|
/* take control over the ports */
|
|
cmd = ehci_readl(&hcor->or_configflag);
|
|
cmd |= FLAG_CF;
|
|
ehci_writel(&hcor->or_configflag, cmd);
|
|
/* unblock posted write */
|
|
cmd = ehci_readl(&hcor->or_usbcmd);
|
|
mdelay(5);
|
|
reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
|
|
printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
|
|
|
|
rootdev = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
|
int length)
|
|
{
|
|
|
|
if (usb_pipetype(pipe) != PIPE_BULK) {
|
|
debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
|
|
return -1;
|
|
}
|
|
return ehci_submit_async(dev, pipe, buffer, length, NULL);
|
|
}
|
|
|
|
int
|
|
submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
|
int length, struct devrequest *setup)
|
|
{
|
|
|
|
if (usb_pipetype(pipe) != PIPE_CONTROL) {
|
|
debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
|
|
return -1;
|
|
}
|
|
|
|
if (usb_pipedevice(pipe) == rootdev) {
|
|
if (!rootdev)
|
|
dev->speed = USB_SPEED_HIGH;
|
|
return ehci_submit_root(dev, pipe, buffer, length, setup);
|
|
}
|
|
return ehci_submit_async(dev, pipe, buffer, length, setup);
|
|
}
|
|
|
|
int
|
|
submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
|
|
int length, int interval)
|
|
{
|
|
debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
|
|
dev, pipe, buffer, length, interval);
|
|
|
|
/*
|
|
* Interrupt transfers requiring several transactions are not supported
|
|
* because bInterval is ignored.
|
|
*
|
|
* Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
|
|
* <= PKT_ALIGN if several qTDs are required, while the USB
|
|
* specification does not constrain this for interrupt transfers. That
|
|
* means that ehci_submit_async() would support interrupt transfers
|
|
* requiring several transactions only as long as the transfer size does
|
|
* not require more than a single qTD.
|
|
*/
|
|
if (length > usb_maxpacket(dev, pipe)) {
|
|
printf("%s: Interrupt transfers requiring several transactions "
|
|
"are not supported.\n", __func__);
|
|
return -1;
|
|
}
|
|
return ehci_submit_async(dev, pipe, buffer, length, NULL);
|
|
}
|