mirror of
https://github.com/brain-hackers/u-boot-brain
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2955d60015
Some Exynos5250 silicon may require 1.05v on the MIF to be stable, so to be safe we can default to 1.05v instead of 1.00v. This can be set optimally later in the boot process by the kernel. The 0x6 value for 1.05v comes from the MAX77686 datasheet. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
193 lines
5.3 KiB
C
193 lines
5.3 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MAX77686_H_
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#define __MAX77686_H_
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enum {
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MAX77686_REG_PMIC_ID = 0x0,
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MAX77686_REG_PMIC_INTSRC,
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MAX77686_REG_PMIC_INT1,
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MAX77686_REG_PMIC_INT2,
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MAX77686_REG_PMIC_INT1MSK,
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MAX77686_REG_PMIC_INT2MSK,
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MAX77686_REG_PMIC_STATUS1,
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MAX77686_REG_PMIC_STATUS2,
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MAX77686_REG_PMIC_PWRON,
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MAX77686_REG_PMIC_ONOFFDELAY,
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MAX77686_REG_PMIC_MRSTB,
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MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
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MAX77686_REG_PMIC_BUCK1OUT,
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MAX77686_REG_PMIC_BUCK2CTRL1,
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MAX77686_REG_PMIC_BUCK234FREQ,
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MAX77686_REG_PMIC_BUCK2DVS1,
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MAX77686_REG_PMIC_BUCK2DVS2,
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MAX77686_REG_PMIC_BUCK2DVS3,
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MAX77686_REG_PMIC_BUCK2DVS4,
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MAX77686_REG_PMIC_BUCK2DVS5,
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MAX77686_REG_PMIC_BUCK2DVS6,
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MAX77686_REG_PMIC_BUCK2DVS7,
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MAX77686_REG_PMIC_BUCK2DVS8,
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MAX77686_REG_PMIC_BUCK3CTRL,
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MAX77686_REG_PMIC_BUCK3DVS1,
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MAX77686_REG_PMIC_BUCK3DVS2,
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MAX77686_REG_PMIC_BUCK3DVS3,
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MAX77686_REG_PMIC_BUCK3DVS4,
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MAX77686_REG_PMIC_BUCK3DVS5,
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MAX77686_REG_PMIC_BUCK3DVS6,
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MAX77686_REG_PMIC_BUCK3DVS7,
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MAX77686_REG_PMIC_BUCK3DVS8,
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MAX77686_REG_PMIC_BUCK4CTRL1,
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MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
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MAX77686_REG_PMIC_BUCK4DVS2,
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MAX77686_REG_PMIC_BUCK4DVS3,
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MAX77686_REG_PMIC_BUCK4DVS4,
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MAX77686_REG_PMIC_BUCK4DVS5,
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MAX77686_REG_PMIC_BUCK4DVS6,
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MAX77686_REG_PMIC_BUCK4DVS7,
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MAX77686_REG_PMIC_BUCK4DVS8,
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MAX77686_REG_PMIC_BUCK5CTRL,
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MAX77686_REG_PMIC_BUCK5OUT,
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MAX77686_REG_PMIC_BUCK6CRTL,
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MAX77686_REG_PMIC_BUCK6OUT,
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MAX77686_REG_PMIC_BUCK7CRTL,
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MAX77686_REG_PMIC_BUCK7OUT,
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MAX77686_REG_PMIC_BUCK8CRTL,
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MAX77686_REG_PMIC_BUCK8OUT,
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MAX77686_REG_PMIC_BUCK9CRTL,
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MAX77686_REG_PMIC_BUCK9OUT,
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MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
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MAX77686_REG_PMIC_LDO2CTRL1,
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MAX77686_REG_PMIC_LDO3CTRL1,
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MAX77686_REG_PMIC_LDO4CTRL1,
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MAX77686_REG_PMIC_LDO5CTRL1,
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MAX77686_REG_PMIC_LDO6CTRL1,
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MAX77686_REG_PMIC_LDO7CTRL1,
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MAX77686_REG_PMIC_LDO8CTRL1,
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MAX77686_REG_PMIC_LDO9CTRL1,
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MAX77686_REG_PMIC_LDO10CTRL1,
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MAX77686_REG_PMIC_LDO11CTRL1,
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MAX77686_REG_PMIC_LDO12CTRL1,
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MAX77686_REG_PMIC_LDO13CTRL1,
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MAX77686_REG_PMIC_LDO14CTRL1,
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MAX77686_REG_PMIC_LDO15CTRL1,
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MAX77686_REG_PMIC_LDO16CTRL1,
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MAX77686_REG_PMIC_LDO17CTRL1,
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MAX77686_REG_PMIC_LDO18CTRL1,
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MAX77686_REG_PMIC_LDO19CTRL1,
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MAX77686_REG_PMIC_LDO20CTRL1,
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MAX77686_REG_PMIC_LDO21CTRL1,
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MAX77686_REG_PMIC_LDO22CTRL1,
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MAX77686_REG_PMIC_LDO23CTRL1,
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MAX77686_REG_PMIC_LDO24CTRL1,
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MAX77686_REG_PMIC_LDO25CTRL1,
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MAX77686_REG_PMIC_LDO26CTRL1,
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MAX77686_REG_PMIC_LDO1CTRL2,
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MAX77686_REG_PMIC_LDO2CTRL2,
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MAX77686_REG_PMIC_LDO3CTRL2,
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MAX77686_REG_PMIC_LDO4CTRL2,
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MAX77686_REG_PMIC_LDO5CTRL2,
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MAX77686_REG_PMIC_LDO6CTRL2,
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MAX77686_REG_PMIC_LDO7CTRL2,
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MAX77686_REG_PMIC_LDO8CTRL2,
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MAX77686_REG_PMIC_LDO9CTRL2,
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MAX77686_REG_PMIC_LDO10CTRL2,
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MAX77686_REG_PMIC_LDO11CTRL2,
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MAX77686_REG_PMIC_LDO12CTRL2,
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MAX77686_REG_PMIC_LDO13CTRL2,
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MAX77686_REG_PMIC_LDO14CTRL2,
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MAX77686_REG_PMIC_LDO15CTRL2,
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MAX77686_REG_PMIC_LDO16CTRL2,
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MAX77686_REG_PMIC_LDO17CTRL2,
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MAX77686_REG_PMIC_LDO18CTRL2,
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MAX77686_REG_PMIC_LDO19CTRL2,
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MAX77686_REG_PMIC_LDO20CTRL2,
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MAX77686_REG_PMIC_LDO21CTRL2,
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MAX77686_REG_PMIC_LDO22CTRL2,
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MAX77686_REG_PMIC_LDO23CTRL2,
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MAX77686_REG_PMIC_LDO24CTRL2,
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MAX77686_REG_PMIC_LDO25CTRL2,
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MAX77686_REG_PMIC_LDO26CTRL2,
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MAX77686_REG_PMIC_BBAT = 0x7e,
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MAX77686_REG_PMIC_32KHZ,
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PMIC_NUM_OF_REGS,
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};
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/* I2C device address for pmic max77686 */
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#define MAX77686_I2C_ADDR (0x12 >> 1)
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enum {
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REG_DISABLE = 0,
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REG_ENABLE
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};
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enum {
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LDO_OFF = 0,
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LDO_ON,
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DIS_LDO = (0x00 << 6),
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EN_LDO = (0x3 << 6),
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};
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/* Buck1 1 volt value */
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#define MAX77686_BUCK1OUT_1V 0x5
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/* Buck1 1.05 volt value */
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#define MAX77686_BUCK1OUT_1_05V 0x6
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#define MAX77686_BUCK1CTRL_EN (3 << 0)
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/* Buck2 1.3 volt value */
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#define MAX77686_BUCK2DVS1_1_3V 0x38
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#define MAX77686_BUCK2CTRL_ON (1 << 4)
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/* Buck3 1.0125 volt value */
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#define MAX77686_BUCK3DVS1_1_0125V 0x21
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#define MAX77686_BUCK3CTRL_ON (1 << 4)
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/* Buck4 1.2 volt value */
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#define MAX77686_BUCK4DVS1_1_2V 0x30
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#define MAX77686_BUCK4CTRL_ON (1 << 4)
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/* LDO2 1.5 volt value */
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#define MAX77686_LD02CTRL1_1_5V 0x1c
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/* LDO3 1.8 volt value */
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#define MAX77686_LD03CTRL1_1_8V 0x14
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/* LDO5 1.8 volt value */
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#define MAX77686_LD05CTRL1_1_8V 0x14
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/* LDO10 1.8 volt value */
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#define MAX77686_LD10CTRL1_1_8V 0x14
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/*
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* MAX77686_REG_PMIC_32KHZ set to 32KH CP
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* output is activated
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*/
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#define MAX77686_32KHCP_EN (1 << 1)
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/*
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* MAX77686_REG_PMIC_BBAT set to
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* Back up batery charger on and
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* limit voltage setting to 3.5v
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*/
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#define MAX77686_BBCHOSTEN (1 << 0)
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#define MAX77686_BBCVS_3_5V (3 << 3)
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#endif /* __MAX77686_PMIC_H_ */
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