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https://github.com/brain-hackers/u-boot-brain
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9c653aad16
Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
163 lines
3.6 KiB
C
163 lines
3.6 KiB
C
/*
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* Board functions for Compulab CM-T335 board
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*
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* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
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*
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* Author: Ilya Ledvich <ilya@compulab.co.il>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware_am33xx.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include "../common/eeprom.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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gpmc_init();
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#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
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status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
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#endif
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return 0;
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}
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#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slave = {
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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.phy_if = PHY_INTERFACE_MODE_RGMII,
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = &cpsw_slave,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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/* PHY reset GPIO */
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#define GPIO_PHY_RST GPIO_PIN(3, 7)
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static void board_phy_init(void)
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{
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gpio_request(GPIO_PHY_RST, "phy_rst");
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gpio_direction_output(GPIO_PHY_RST, 0);
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mdelay(2);
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gpio_set_value(GPIO_PHY_RST, 1);
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mdelay(2);
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}
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static void get_efuse_mac_addr(uchar *enetaddr)
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{
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uint32_t mac_hi, mac_lo;
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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enetaddr[0] = mac_hi & 0xFF;
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enetaddr[1] = (mac_hi & 0xFF00) >> 8;
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enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
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enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
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enetaddr[4] = mac_lo & 0xFF;
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enetaddr[5] = (mac_lo & 0xFF00) >> 8;
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}
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/*
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* Routine: handle_mac_address
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* Description: prepare MAC address for on-board Ethernet.
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*/
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static int handle_mac_address(void)
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{
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uchar enetaddr[6];
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int rv;
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rv = eth_getenv_enetaddr("ethaddr", enetaddr);
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if (rv)
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return 0;
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rv = cl_eeprom_read_mac_addr(enetaddr);
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if (rv)
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get_efuse_mac_addr(enetaddr);
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if (!is_valid_ether_addr(enetaddr))
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return -1;
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return eth_setenv_enetaddr("ethaddr", enetaddr);
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}
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#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
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#define AR8051_PHY_DEBUG_DATA_REG 0x1e
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#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
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#define AR8051_RGMII_TX_CLK_DLY 0x100
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int board_eth_init(bd_t *bis)
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{
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int rv, n = 0;
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const char *devname;
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struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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rv = handle_mac_address();
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if (rv)
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printf("No MAC address found!\n");
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writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
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board_phy_init();
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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/*
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* CPSW RGMII Internal Delay Mode is not supported in all PVT
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* operating points. So we must set the TX clock delay feature
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* in the AR8051 PHY. Since we only support a single ethernet
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* device, we only do this for the first instance.
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*/
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devname = miiphy_get_current_dev();
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miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
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AR8051_DEBUG_RGMII_CLK_DLY_REG);
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miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
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AR8051_RGMII_TX_CLK_DLY);
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return n;
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}
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#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
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