mirror of
https://github.com/brain-hackers/u-boot-brain
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0a9ef45158
This converts the following to Kconfig:
CONFIG_NAND_MXC
CONFIG_NAND_OMAP_GPMC
CONFIG_NAND_OMAP_GPMC_PREFETCH
CONFIG_NAND_OMAP_ELM
CONFIG_SPL_NAND_AM33XX_BCH
CONFIG_SPL_NAND_SIMPLE
CONFIG_SYS_NAND_BUSWIDTH_16BIT
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Finish migration of CONFIG_SPL_NAND_SIMPLE, fix some build issues,
add CONFIG_NAND_MXC so we can do CONFIG_SYS_NAND_BUSWIDTH_16BIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
34 lines
868 B
C
34 lines
868 B
C
/*
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* ti_armv7_omap.h
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* The various ARMv7 SoCs from TI all share a number of IP blocks when
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* implementing a given feature. This is meant to isolate the features
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* that are based on OMAP architecture.
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*/
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#ifndef __CONFIG_TI_ARMV7_OMAP_H__
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#define __CONFIG_TI_ARMV7_OMAP_H__
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/* I2C IP block */
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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/*
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* GPMC NAND block. We support 1 device and the physical address to
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* access CS0 at is 0x8000000.
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*/
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#ifdef CONFIG_NAND
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#ifndef CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_BASE 0x8000000
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#endif
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#endif
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/* Now for the remaining common defines */
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#include <configs/ti_armv7_common.h>
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#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */
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