mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
616aa55d17
Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
70 lines
1.4 KiB
C
70 lines
1.4 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX7.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX7_COMMON_H
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#define __MX7_COMMON_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/mach-imx/gpio.h>
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#ifndef CONFIG_MX7
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#define CONFIG_MX7
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#endif
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/* Timer settings */
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#define CONFIG_MXC_GPT_HCLK
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#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
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#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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/* Enable iomux-lpsr support */
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#define CONFIG_IOMUX_LPSR
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#define CONFIG_LOADADDR 0x80800000
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#define CONFIG_SYS_TEXT_BASE 0x87800000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 512
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#define CONFIG_SYS_MAXARGS 32
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#ifndef CONFIG_SYS_DCACHE_OFF
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#endif
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/* GPIO */
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#define CONFIG_MXC_GPIO
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/* UART */
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#define CONFIG_MXC_UART
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/* MMC */
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_FSL_ESDHC
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#define CONFIG_FSL_USDHC
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/* Fuses */
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#define CONFIG_MXC_OCOTP
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#define CONFIG_ARMV7_SECURE_BASE 0x00900000
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/* Secure boot (HAB) support */
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_CSF_SIZE 0x2000
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#endif
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#endif
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