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![Patrick Delaunay](/assets/img/avatar_default.png)
Replace the psci_save_target_pc call by the new function psci_save(cpu, pc,context_id) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
258 lines
5.1 KiB
ArmAsm
258 lines
5.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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* Author: Wang Dongsheng <dongsheng.wang@freescale.com>
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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#include <asm/arch-armv7/generictimer.h>
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#include <asm/psci.h>
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#define RCPM_TWAITSR 0x04C
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#define SCFG_CORE0_SFT_RST 0x130
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#define SCFG_CORESRENCR 0x204
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#define DCFG_CCSR_RSTCR 0x0B0
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#define DCFG_CCSR_RSTCR_RESET_REQ 0x2
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#define DCFG_CCSR_BRR 0x0E4
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#define DCFG_CCSR_SCRATCHRW1 0x200
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#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
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#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
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#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
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#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
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#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
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#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
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#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
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#define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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.align 5
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#define ONE_MS (COUNTER_FREQUENCY / 1000)
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#define RESET_WAIT (30 * ONE_MS)
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.globl psci_version
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psci_version:
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movw r0, #0
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movt r0, #1
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bx lr
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_ls102x_psci_supported_table:
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.word ARM_PSCI_0_2_FN_PSCI_VERSION
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.word PSCI_FN_PSCI_VERSION_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_CPU_SUSPEND
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.word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_CPU_OFF
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.word PSCI_FN_CPU_OFF_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_CPU_ON
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.word PSCI_FN_CPU_ON_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_AFFINITY_INFO
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.word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_SYSTEM_OFF
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.word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
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.word ARM_PSCI_0_2_FN_SYSTEM_RESET
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.word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
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.word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
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.word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
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.word 0
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.word ARM_PSCI_RET_NI
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.globl psci_features
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psci_features:
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adr r2, _ls102x_psci_supported_table
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1: ldr r3, [r2]
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cmp r3, #0
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beq out_psci_features
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cmp r1, r3
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addne r2, r2, #8
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bne 1b
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out_psci_features:
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ldr r0, [r2, #4]
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bx lr
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@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
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@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
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@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
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@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
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LENTRY(psci_check_target_cpu_id)
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@ Get the real CPU number
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and r4, r1, #0xff
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mov r0, #ARM_PSCI_RET_INVAL
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@ Bit[31:24], bits must be zero.
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tst r1, #0xff000000
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bxne lr
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@ Affinity level 2 - Cluster: only one cluster in LS1021xa.
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tst r1, #0xff0000
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bxne lr
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@ Affinity level 1 - Processors: should be in 0xf00 format.
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lsr r1, r1, #8
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teq r1, #0xf
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bxne lr
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@ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
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cmp r4, #2
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bxge lr
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mov r0, #ARM_PSCI_RET_SUCCESS
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bx lr
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ENDPROC(psci_check_target_cpu_id)
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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push {r4, r5, r6, lr}
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@ Clear and Get the correct CPU number
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@ r1 = 0xf01
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bl psci_check_target_cpu_id
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cmp r0, #ARM_PSCI_RET_INVAL
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beq out_psci_cpu_on
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mov r0, r4
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mov r1, r2
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mov r2, r3
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bl psci_save
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mov r1, r4
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@ Get DCFG base address
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movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
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movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
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@ Detect target CPU state
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ldr r2, [r4, #DCFG_CCSR_BRR]
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rev r2, r2
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lsr r2, r2, r1
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ands r2, r2, #1
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beq holdoff_release
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@ Reset target CPU
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@ Get SCFG base address
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movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
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movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
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@ Enable CORE Soft Reset
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movw r5, #0
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movt r5, #(1 << 15)
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rev r5, r5
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str r5, [r0, #SCFG_CORESRENCR]
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@ Get CPUx offset register
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mov r6, #0x4
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mul r6, r6, r1
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add r2, r0, r6
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@ Do reset on target CPU
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movw r5, #0
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movt r5, #(1 << 15)
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rev r5, r5
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str r5, [r2, #SCFG_CORE0_SFT_RST]
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@ Wait target CPU up
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timer_wait r2, RESET_WAIT
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@ Disable CORE soft reset
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mov r5, #0
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str r5, [r0, #SCFG_CORESRENCR]
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holdoff_release:
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@ Release on target CPU
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ldr r2, [r4, #DCFG_CCSR_BRR]
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mov r6, #1
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lsl r6, r6, r1 @ 32 bytes per CPU
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rev r6, r6
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orr r2, r2, r6
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str r2, [r4, #DCFG_CCSR_BRR]
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@ Set secondary boot entry
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ldr r6, =psci_cpu_entry
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rev r6, r6
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str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
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isb
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dsb
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@ Return
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mov r0, #ARM_PSCI_RET_SUCCESS
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out_psci_cpu_on:
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pop {r4, r5, r6, lr}
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bx lr
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.globl psci_cpu_off
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psci_cpu_off:
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bl psci_cpu_off_common
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1: wfi
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b 1b
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.globl psci_affinity_info
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psci_affinity_info:
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push {lr}
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mov r0, #ARM_PSCI_RET_INVAL
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@ Verify Affinity level
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cmp r2, #0
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bne out_affinity_info
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bl psci_check_target_cpu_id
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cmp r0, #ARM_PSCI_RET_INVAL
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beq out_affinity_info
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mov r1, r4
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@ Get RCPM base address
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movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
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movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
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mov r0, #PSCI_AFFINITY_LEVEL_ON
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@ Detect target CPU state
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ldr r2, [r4, #RCPM_TWAITSR]
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rev r2, r2
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lsr r2, r2, r1
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ands r2, r2, #1
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beq out_affinity_info
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mov r0, #PSCI_AFFINITY_LEVEL_OFF
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out_affinity_info:
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pop {pc}
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.globl psci_system_reset
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psci_system_reset:
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@ Get DCFG base address
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movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
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movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
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mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
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rev r2, r2
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str r2, [r1, #DCFG_CCSR_RSTCR]
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1: wfi
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b 1b
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.globl psci_system_suspend
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psci_system_suspend:
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push {lr}
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bl ls1_system_suspend
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pop {pc}
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.popsection
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