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- Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
807 lines
23 KiB
C
807 lines
23 KiB
C
/**
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* @file IxNpeDlNpeMgrUtils.c
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*
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* @author Intel Corporation
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* @date 18 February 2002
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*
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* @brief This file contains the implementation of the private API for the
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* IXP425 NPE Downloader NpeMgr Utils module
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*
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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/*
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* Put the system defined include files required.
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*/
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#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of
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* retries before
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* timeout
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*/
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/*
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* Put the user defined include files required.
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*/
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#include "IxOsal.h"
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#include "IxNpeDl.h"
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#include "IxNpeDlNpeMgrUtils_p.h"
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#include "IxNpeDlNpeMgrEcRegisters_p.h"
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#include "IxNpeDlMacros_p.h"
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/*
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* #defines and macros used in this file.
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*/
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/* used to bit-mask a number of bytes */
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#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF
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#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF
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#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF
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#define IX_NPEDL_BYTES_PER_WORD 4
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#define IX_NPEDL_BYTES_PER_SHORT 2
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#define IX_NPEDL_REG_SIZE_BYTE 8
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#define IX_NPEDL_REG_SIZE_SHORT 16
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#define IX_NPEDL_REG_SIZE_WORD 32
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/*
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* Introduce extra read cycles after issuing read command to NPE
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* so that we read the register after the NPE has updated it
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* This is to overcome race condition between XScale and NPE
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*/
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#define IX_NPEDL_DELAY_READ_CYCLES 2
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/*
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* To mask top three MSBs of 32bit word to download into NPE IMEM
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*/
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#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF;
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/*
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* typedefs
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*/
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typedef struct
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{
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UINT32 regAddress;
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UINT32 regSize;
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} IxNpeDlCtxtRegAccessInfo;
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/* module statistics counters */
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typedef struct
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{
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UINT32 insMemWrites;
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UINT32 insMemWriteFails;
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UINT32 dataMemWrites;
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UINT32 dataMemWriteFails;
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UINT32 ecsRegWrites;
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UINT32 ecsRegReads;
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UINT32 dbgInstructionExecs;
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UINT32 contextRegWrites;
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UINT32 physicalRegWrites;
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UINT32 nextPcWrites;
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} IxNpeDlNpeMgrUtilsStats;
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/*
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* Variable declarations global to this file only. Externs are followed by
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* static variables.
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*/
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/*
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* contains useful address and function pointers to read/write Context Regs,
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* eliminating some switch or if-else statements in places
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*/
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static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] =
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{
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{
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IX_NPEDL_CTXT_REG_ADDR_STEVT,
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IX_NPEDL_REG_SIZE_BYTE
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},
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{
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IX_NPEDL_CTXT_REG_ADDR_STARTPC,
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IX_NPEDL_REG_SIZE_SHORT
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},
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{
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IX_NPEDL_CTXT_REG_ADDR_REGMAP,
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IX_NPEDL_REG_SIZE_SHORT
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},
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{
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IX_NPEDL_CTXT_REG_ADDR_CINDEX,
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IX_NPEDL_REG_SIZE_BYTE
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}
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};
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static UINT32 ixNpeDlSavedExecCount = 0;
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static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0;
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static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats;
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/*
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* static function prototypes.
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*/
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PRIVATE __inline__ void
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ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd,
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UINT32 addr, UINT32 data);
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PRIVATE __inline__ UINT32
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ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr);
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr,
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UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal);
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr,
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UINT32 regVal, UINT32 regSize,
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UINT32 ctxtNum, BOOL verify);
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/*
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* Function definition: ixNpeDlNpeMgrWriteCommandIssue
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*/
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PRIVATE __inline__ void
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ixNpeDlNpeMgrWriteCommandIssue (
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UINT32 npeBaseAddress,
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UINT32 cmd,
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UINT32 addr,
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UINT32 data)
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{
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data);
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
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}
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/*
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* Function definition: ixNpeDlNpeMgrReadCommandIssue
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*/
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PRIVATE __inline__ UINT32
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ixNpeDlNpeMgrReadCommandIssue (
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UINT32 npeBaseAddress,
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UINT32 cmd,
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UINT32 addr)
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{
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UINT32 data = 0;
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int i;
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr);
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
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for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++)
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{
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IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data);
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}
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return data;
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}
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/*
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* Function definition: ixNpeDlNpeMgrInsMemWrite
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*/
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IX_STATUS
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ixNpeDlNpeMgrInsMemWrite (
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UINT32 npeBaseAddress,
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UINT32 insMemAddress,
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UINT32 insMemData,
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BOOL verify)
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{
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UINT32 insMemDataRtn;
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ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_WR_INS_MEM,
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insMemAddress, insMemData);
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if (verify)
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{
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/* write invalid data to this reg, so we can see if we're reading
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the EXDATA register too early */
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA,
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~insMemData);
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/*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/
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insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
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insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
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insMemAddress);
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insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS;
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if (insMemData != insMemDataRtn)
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{
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ixNpeDlNpeMgrUtilsStats.insMemWriteFails++;
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return IX_FAIL;
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}
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}
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ixNpeDlNpeMgrUtilsStats.insMemWrites++;
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return IX_SUCCESS;
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}
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/*
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* Function definition: ixNpeDlNpeMgrDataMemWrite
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*/
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IX_STATUS
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ixNpeDlNpeMgrDataMemWrite (
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UINT32 npeBaseAddress,
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UINT32 dataMemAddress,
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UINT32 dataMemData,
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BOOL verify)
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{
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ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_WR_DATA_MEM,
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dataMemAddress, dataMemData);
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if (verify)
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{
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/* write invalid data to this reg, so we can see if we're reading
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the EXDATA register too early */
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData);
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if (dataMemData !=
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ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_RD_DATA_MEM,
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dataMemAddress))
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{
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ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++;
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return IX_FAIL;
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}
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}
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ixNpeDlNpeMgrUtilsStats.dataMemWrites++;
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return IX_SUCCESS;
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}
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/*
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* Function definition: ixNpeDlNpeMgrExecAccRegWrite
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*/
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void
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ixNpeDlNpeMgrExecAccRegWrite (
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UINT32 npeBaseAddress,
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UINT32 regAddress,
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UINT32 regData)
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{
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ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_WR_ECS_REG,
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regAddress, regData);
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ixNpeDlNpeMgrUtilsStats.ecsRegWrites++;
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}
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/*
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* Function definition: ixNpeDlNpeMgrExecAccRegRead
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*/
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UINT32
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ixNpeDlNpeMgrExecAccRegRead (
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UINT32 npeBaseAddress,
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UINT32 regAddress)
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{
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ixNpeDlNpeMgrUtilsStats.ecsRegReads++;
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return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress,
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IX_NPEDL_EXCTL_CMD_RD_ECS_REG,
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regAddress);
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}
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/*
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* Function definition: ixNpeDlNpeMgrCommandIssue
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*/
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void
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ixNpeDlNpeMgrCommandIssue (
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UINT32 npeBaseAddress,
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UINT32 command)
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{
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Entering ixNpeDlNpeMgrCommandIssue\n");
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command);
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Exiting ixNpeDlNpeMgrCommandIssue\n");
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}
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/*
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* Function definition: ixNpeDlNpeMgrDebugInstructionPreExec
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*/
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void
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ixNpeDlNpeMgrDebugInstructionPreExec(
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UINT32 npeBaseAddress)
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{
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/* turn off the halt bit by clearing Execution Count register. */
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/* save reg contents 1st and restore later */
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IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
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&ixNpeDlSavedExecCount);
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0);
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/* ensure that IF and IE are on (temporarily), so that we don't end up
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* stepping forever */
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ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
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IX_NPEDL_ECS_DBG_CTXT_REG_2);
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
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(ixNpeDlSavedEcsDbgCtxtReg2 |
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IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
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IX_NPEDL_MASK_ECS_DBG_REG_2_IE));
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}
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/*
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* Function definition: ixNpeDlNpeMgrDebugInstructionExec
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*/
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IX_STATUS
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ixNpeDlNpeMgrDebugInstructionExec(
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UINT32 npeBaseAddress,
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UINT32 npeInstruction,
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UINT32 ctxtNum,
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UINT32 ldur)
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{
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UINT32 ecsDbgRegVal;
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UINT32 oldWatchcount, newWatchcount;
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UINT32 retriesCount = 0;
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IX_STATUS status = IX_SUCCESS;
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Entering ixNpeDlNpeMgrDebugInstructionExec\n");
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/* set the Active bit, and the LDUR, in the debug level */
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ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE |
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(ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR);
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
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ecsDbgRegVal);
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/*
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* set CCTXT at ECS DEBUG L3 to specify in which context to execute the
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* instruction, and set SELCTXT at ECS DEBUG Level to specify which context
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* store to access.
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* Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
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*/
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ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) |
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(ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT);
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1,
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ecsDbgRegVal);
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/* clear the pipeline */
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ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
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/* load NPE instruction into the instruction register */
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG,
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npeInstruction);
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/* we need this value later to wait for completion of NPE execution step */
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IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount);
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/* issue a Step One command via the Execution Control register */
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ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP);
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/* Watch Count register increments when NPE completes an instruction */
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IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
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&newWatchcount);
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/*
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* force the XScale to wait until the NPE has finished execution step
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* NOTE that this delay will be very small, just long enough to allow a
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* single NPE instruction to complete execution; if instruction execution
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* is not completed before timeout retries, exit the while loop
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*/
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while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
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&& (newWatchcount == oldWatchcount))
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{
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/* Watch Count register increments when NPE completes an instruction */
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IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC,
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&newWatchcount);
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retriesCount++;
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}
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if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount)
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{
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ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++;
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}
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else
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{
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/* Return timeout status as the instruction has not been executed
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* after maximum retries */
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status = IX_NPEDL_CRITICAL_NPE_ERR;
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}
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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"Exiting ixNpeDlNpeMgrDebugInstructionExec\n");
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return status;
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}
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/*
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* Function definition: ixNpeDlNpeMgrDebugInstructionPostExec
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*/
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void
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ixNpeDlNpeMgrDebugInstructionPostExec(
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UINT32 npeBaseAddress)
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{
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/* clear active bit in debug level */
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0,
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0);
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/* clear the pipeline */
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ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
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/* restore Execution Count register contents. */
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IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT,
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ixNpeDlSavedExecCount);
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/* restore IF and IE bits to original values */
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ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2,
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ixNpeDlSavedEcsDbgCtxtReg2);
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}
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/*
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* Function definition: ixNpeDlNpeMgrLogicalRegRead
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*/
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PRIVATE IX_STATUS
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ixNpeDlNpeMgrLogicalRegRead (
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UINT32 npeBaseAddress,
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UINT32 regAddr,
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UINT32 regSize,
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UINT32 ctxtNum,
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UINT32 *regVal)
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{
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IX_STATUS status = IX_SUCCESS;
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UINT32 npeInstruction = 0;
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UINT32 mask = 0;
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IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
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|
"Entering ixNpeDlNpeMgrLogicalRegRead\n");
|
|
|
|
switch (regSize)
|
|
{
|
|
case IX_NPEDL_REG_SIZE_BYTE:
|
|
npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE;
|
|
mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
|
|
case IX_NPEDL_REG_SIZE_SHORT:
|
|
npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT;
|
|
mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
|
|
case IX_NPEDL_REG_SIZE_WORD:
|
|
npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD;
|
|
mask = IX_NPEDL_MASK_FULL_WORD; break;
|
|
}
|
|
|
|
/* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */
|
|
npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) |
|
|
(regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
|
|
|
|
/* step execution of NPE intruction using Debug Executing Context stack */
|
|
status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction,
|
|
ctxtNum, IX_NPEDL_RD_INSTR_LDUR);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
/* read value of register from Execution Data register */
|
|
IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal);
|
|
|
|
/* align value from left to right */
|
|
*regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrLogicalRegRead\n");
|
|
|
|
return IX_SUCCESS;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrLogicalRegWrite
|
|
*/
|
|
PRIVATE IX_STATUS
|
|
ixNpeDlNpeMgrLogicalRegWrite (
|
|
UINT32 npeBaseAddress,
|
|
UINT32 regAddr,
|
|
UINT32 regVal,
|
|
UINT32 regSize,
|
|
UINT32 ctxtNum,
|
|
BOOL verify)
|
|
{
|
|
UINT32 npeInstruction = 0;
|
|
UINT32 mask = 0;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
UINT32 retRegVal;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrLogicalRegWrite\n");
|
|
|
|
if (regSize == IX_NPEDL_REG_SIZE_WORD)
|
|
{
|
|
/* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */
|
|
/* Write upper half-word (short) to |d0|d1| */
|
|
status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr,
|
|
regVal >> IX_NPEDL_REG_SIZE_SHORT,
|
|
IX_NPEDL_REG_SIZE_SHORT,
|
|
ctxtNum, verify);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
|
|
/* Write lower half-word (short) to |d2|d3| */
|
|
status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
|
|
regAddr + IX_NPEDL_BYTES_PER_SHORT,
|
|
regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD,
|
|
IX_NPEDL_REG_SIZE_SHORT,
|
|
ctxtNum, verify);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (regSize)
|
|
{
|
|
case IX_NPEDL_REG_SIZE_BYTE:
|
|
npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
|
|
mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break;
|
|
case IX_NPEDL_REG_SIZE_SHORT:
|
|
npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT;
|
|
mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break;
|
|
}
|
|
/* mask out any redundant bits, so verify will work later */
|
|
regVal &= mask;
|
|
|
|
/* fill dest operand field of instruction with destination reg addr */
|
|
npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST);
|
|
|
|
/* fill src operand field of instruction with least-sig 5 bits of val*/
|
|
npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) <<
|
|
IX_NPEDL_OFFSET_INSTR_SRC);
|
|
|
|
/* fill coprocessor field of instruction with most-sig 11 bits of val*/
|
|
npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
|
|
IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
|
|
|
|
/* step execution of NPE intruction using Debug ECS */
|
|
status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction,
|
|
ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
|
|
|
|
if (IX_SUCCESS != status)
|
|
{
|
|
return status;
|
|
}
|
|
}/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */
|
|
|
|
if (verify)
|
|
{
|
|
status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
|
|
regSize, ctxtNum, &retRegVal);
|
|
|
|
if (IX_SUCCESS == status)
|
|
{
|
|
if (regVal != retRegVal)
|
|
{
|
|
status = IX_FAIL;
|
|
}
|
|
}
|
|
}
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n",
|
|
status);
|
|
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrPhysicalRegWrite
|
|
*/
|
|
IX_STATUS
|
|
ixNpeDlNpeMgrPhysicalRegWrite (
|
|
UINT32 npeBaseAddress,
|
|
UINT32 regAddr,
|
|
UINT32 regValue,
|
|
BOOL verify)
|
|
{
|
|
IX_STATUS status;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrPhysicalRegWrite\n");
|
|
|
|
/*
|
|
* There are 32 physical registers used in an NPE. These are
|
|
* treated as 16 pairs of 32-bit registers. To write one of the pair,
|
|
* write the pair number (0-16) to the REGMAP for Context 0. Then write
|
|
* the value to register 0 or 4 in the regfile, depending on which
|
|
* register of the pair is to be written
|
|
*/
|
|
|
|
/*
|
|
* set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16)
|
|
* of physical registers to write
|
|
*/
|
|
status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress,
|
|
IX_NPEDL_CTXT_REG_ADDR_REGMAP,
|
|
(regAddr >>
|
|
IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP),
|
|
IX_NPEDL_REG_SIZE_SHORT, 0, verify);
|
|
if (status == IX_SUCCESS)
|
|
{
|
|
/* regAddr = 0 or 4 */
|
|
regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
|
|
IX_NPEDL_BYTES_PER_WORD;
|
|
|
|
status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue,
|
|
IX_NPEDL_REG_SIZE_WORD, 0, verify);
|
|
}
|
|
|
|
if (status != IX_SUCCESS)
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: "
|
|
"error writing to physical register\n");
|
|
}
|
|
|
|
ixNpeDlNpeMgrUtilsStats.physicalRegWrites++;
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n",
|
|
status);
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrCtxtRegWrite
|
|
*/
|
|
IX_STATUS
|
|
ixNpeDlNpeMgrCtxtRegWrite (
|
|
UINT32 npeBaseAddress,
|
|
UINT32 ctxtNum,
|
|
IxNpeDlCtxtRegNum ctxtReg,
|
|
UINT32 ctxtRegVal,
|
|
BOOL verify)
|
|
{
|
|
UINT32 tempRegVal;
|
|
UINT32 ctxtRegAddr;
|
|
UINT32 ctxtRegSize;
|
|
IX_STATUS status = IX_SUCCESS;
|
|
|
|
IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Entering ixNpeDlNpeMgrCtxtRegWrite\n");
|
|
|
|
/*
|
|
* Context 0 has no STARTPC. Instead, this value is used to set
|
|
* NextPC for Background ECS, to set where NPE starts executing code
|
|
*/
|
|
if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC))
|
|
{
|
|
/* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */
|
|
tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress,
|
|
IX_NPEDL_ECS_BG_CTXT_REG_0);
|
|
tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
|
|
tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) &
|
|
IX_NPEDL_MASK_ECS_REG_0_NEXTPC;
|
|
|
|
ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress,
|
|
IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal);
|
|
|
|
ixNpeDlNpeMgrUtilsStats.nextPcWrites++;
|
|
}
|
|
else
|
|
{
|
|
ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress;
|
|
ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize;
|
|
status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr,
|
|
ctxtRegVal, ctxtRegSize,
|
|
ctxtNum, verify);
|
|
if (status != IX_SUCCESS)
|
|
{
|
|
IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: "
|
|
"error writing to context store register\n");
|
|
}
|
|
|
|
ixNpeDlNpeMgrUtilsStats.contextRegWrites++;
|
|
}
|
|
|
|
IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT,
|
|
"Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n",
|
|
status);
|
|
|
|
return status;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrUtilsStatsShow
|
|
*/
|
|
void
|
|
ixNpeDlNpeMgrUtilsStatsShow (void)
|
|
{
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER,
|
|
IX_OSAL_LOG_DEV_STDOUT,
|
|
"\nixNpeDlNpeMgrUtilsStatsShow:\n"
|
|
"\tInstruction Memory writes: %u\n"
|
|
"\tInstruction Memory writes failed: %u\n"
|
|
"\tData Memory writes: %u\n"
|
|
"\tData Memory writes failed: %u\n",
|
|
ixNpeDlNpeMgrUtilsStats.insMemWrites,
|
|
ixNpeDlNpeMgrUtilsStats.insMemWriteFails,
|
|
ixNpeDlNpeMgrUtilsStats.dataMemWrites,
|
|
ixNpeDlNpeMgrUtilsStats.dataMemWriteFails,
|
|
0,0);
|
|
|
|
ixOsalLog (IX_OSAL_LOG_LVL_USER,
|
|
IX_OSAL_LOG_DEV_STDOUT,
|
|
"\tExecuting Context Stack Register writes: %u\n"
|
|
"\tExecuting Context Stack Register reads: %u\n"
|
|
"\tPhysical Register writes: %u\n"
|
|
"\tContext Store Register writes: %u\n"
|
|
"\tExecution Backgound Context NextPC writes: %u\n"
|
|
"\tDebug Instructions Executed: %u\n\n",
|
|
ixNpeDlNpeMgrUtilsStats.ecsRegWrites,
|
|
ixNpeDlNpeMgrUtilsStats.ecsRegReads,
|
|
ixNpeDlNpeMgrUtilsStats.physicalRegWrites,
|
|
ixNpeDlNpeMgrUtilsStats.contextRegWrites,
|
|
ixNpeDlNpeMgrUtilsStats.nextPcWrites,
|
|
ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs);
|
|
}
|
|
|
|
|
|
/*
|
|
* Function definition: ixNpeDlNpeMgrUtilsStatsReset
|
|
*/
|
|
void
|
|
ixNpeDlNpeMgrUtilsStatsReset (void)
|
|
{
|
|
ixNpeDlNpeMgrUtilsStats.insMemWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0;
|
|
ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0;
|
|
ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0;
|
|
ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0;
|
|
ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0;
|
|
}
|