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https://github.com/brain-hackers/u-boot-brain
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b95611f67e
The FSP-S changes the ITSS priorities. The code that tries to save it before running FSP-S and restore it afterwards does not work as U-Boot relocates in between the save and restore. This means that the driver data saved before relocation is lost and the new driver just sees zeroes. Fix this by allocating space in the relocated memory for the ITSS data. Save it there and access it from the driver after relocation. This fixes interrupt handling on coral. Also drop the log_msg_ret() in irq_first_device_type() since this function can be called speculatively in places where we are not sure if there is an interrupt controller of that type. The resulting log errors are confusing when there is no error. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Interrupt Timer Subsystem
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*
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* Copyright (C) 2017 Intel Corporation.
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot itss.h
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*/
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#ifndef _ASM_ARCH_ITSS_H
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#define _ASM_ARCH_ITSS_H
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#define GPIO_IRQ_START 50
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#define GPIO_IRQ_END ITSS_MAX_IRQ
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#define ITSS_MAX_IRQ 119
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#define IRQS_PER_IPC 32
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#define NUM_IPC_REGS DIV_ROUND_UP(ITSS_MAX_IRQ, IRQS_PER_IPC)
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/* Max PXRC registers in ITSS */
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#define MAX_PXRC_CONFIG (PCR_ITSS_PIRQH_ROUT - PCR_ITSS_PIRQA_ROUT + 1)
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/* PIRQA Routing Control Register */
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#define PCR_ITSS_PIRQA_ROUT 0x3100
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/* PIRQB Routing Control Register */
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#define PCR_ITSS_PIRQB_ROUT 0x3101
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/* PIRQC Routing Control Register */
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#define PCR_ITSS_PIRQC_ROUT 0x3102
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/* PIRQD Routing Control Register */
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#define PCR_ITSS_PIRQD_ROUT 0x3103
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/* PIRQE Routing Control Register */
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#define PCR_ITSS_PIRQE_ROUT 0x3104
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/* PIRQF Routing Control Register */
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#define PCR_ITSS_PIRQF_ROUT 0x3105
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/* PIRQG Routing Control Register */
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#define PCR_ITSS_PIRQG_ROUT 0x3106
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/* PIRQH Routing Control Register */
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#define PCR_ITSS_PIRQH_ROUT 0x3107
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/* ITSS Interrupt polarity control */
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#define PCR_ITSS_IPC0_CONF 0x3200
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/* ITSS Power reduction control */
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#define PCR_ITSS_ITSSPRC 0x3300
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#endif /* _ASM_ARCH_ITSS_H */
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