mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
54055ff7a6
The check for the missing PEX switch can lead to an infinite loop, when the PCIe device is not found. It is helpful to enable the user to break out of this boot-loop, to enable booting to the prompt for test cases. This patch adds a 3 second delay in the error case before rebooting. The user can press Ctrl-C in this time to abort the boot-loop. This patch also calls bootcount_inc() before rebooting in the error case. This is needed to increment the bootcounter, since this function is called earlier than the main bootcounter increment. Otherwise the bootcounter will not be incremented in the error case at all. Signed-off-by: Stefan Roese <sr@denx.de>
349 lines
9.6 KiB
C
349 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2019 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <console.h>
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#include <i2c.h>
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#include <pci.h>
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#if !defined(CONFIG_SPL_BUILD)
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#include <bootcount.h>
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#endif
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/crc8.h>
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#include <linux/mbus.h>
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#ifdef CONFIG_NET
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#include <netdev.h>
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#endif
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#include "theadorable.h"
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#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
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#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
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#define PHY_CHANNEL_RX_CTRL0_REG(port, chan) \
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(MV_USB_PHY_BASE + ((port) << 12) + ((chan) << 6) + 0x8)
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#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
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#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
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#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
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#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
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#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
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#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
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#define GPIO_USB0_PWR_ON 18
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#define GPIO_USB1_PWR_ON 19
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#define PEX_SWITCH_NOT_FOUNT_LIMIT 3
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#define STM_I2C_BUS 1
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#define STM_I2C_ADDR 0x27
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#define REBOOT_DELAY 1000 /* reboot-delay in ms */
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#define ABORT_TIMEOUT 3000 /* 3 seconds reboot abort timeout */
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/* DDR3 static configuration */
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static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
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{0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
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{0x00001404, 0x30000800}, /* Dunit Control Low Register */
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{0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
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{0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
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{0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
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{0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
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{0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
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{0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
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{0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
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{0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
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{0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
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{0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
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{0x000014A8, 0x00000101}, /* AXI Control Register */
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/*
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* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
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* training sequence
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*/
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{0x000200e8, 0x3fff0e01},
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{0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
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{0x0001504, 0x7fffffe1}, /* CS0 Size */
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{0x000150C, 0x00000000}, /* CS1 Size */
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{0x0001514, 0x00000000}, /* CS2 Size */
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{0x000151C, 0x00000000}, /* CS3 Size */
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{0x00020220, 0x00000007}, /* Reserved */
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{0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
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{0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
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{0x000015D0, 0x00000650}, /* MR0 */
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{0x000015D4, 0x00000044}, /* MR1 */
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{0x000015D8, 0x00000010}, /* MR2 */
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{0x000015DC, 0x00000000}, /* MR3 */
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{0x000015E0, 0x00000001},
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{0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
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{0x000015EC, 0xf800a225}, /* DDR PHY */
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/* Recommended Settings from Marvell for 4 x 16 bit devices: */
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{0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
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{0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
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{0x0, 0x0}
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};
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static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
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{"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
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};
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extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
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/*
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* Lane0 - PCIE0.0 X1 (to WIFI Module)
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* Lane5 - SATA0
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* Lane6 - SATA1
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* Lane7 - SGMII0 (to Ethernet Phy)
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* Lane8-11 - PCIE2.0 X4 (to PEX Switch)
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* all other lanes are disabled
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*/
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MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
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{ MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
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{ PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
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PEX_BUS_DISABLED },
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0x0060, serdes_change_m_phy
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},
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};
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/*
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* Define a board-specific detection pulse-width array for the SerDes PCIe
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* interfaces. If not defined in the board code, the default of currently 2
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* is used. Values from 0...3 are possible (2 bits).
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*/
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u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
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MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
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{
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/* Only one mode supported for this board */
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return &board_ddr_modes[0];
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}
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MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
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{
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return &theadorable_serdes_cfg[0];
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}
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u8 board_sat_r_get(u8 dev_num, u8 reg)
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{
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/* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
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return 0x01;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x00000000, MVEBU_MPP_BASE + 0x00);
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writel(0x03300000, MVEBU_MPP_BASE + 0x04);
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writel(0x00000033, MVEBU_MPP_BASE + 0x08);
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writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
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writel(0x11110000, MVEBU_MPP_BASE + 0x10);
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writel(0x00221100, MVEBU_MPP_BASE + 0x14);
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writel(0x00000000, MVEBU_MPP_BASE + 0x18);
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writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
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writel(0x00000000, MVEBU_MPP_BASE + 0x20);
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/* Configure GPIO */
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writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
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writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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int ret;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/*
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* Map SPI devices via MBUS so that they can be accessed via
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* the SPI direct access mode
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*/
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mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
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mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
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/*
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* Set RX Channel Control 0 Register:
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* Tests have shown, that setting the LPF_COEF from 0 (1/8)
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* to 3 (1/1) results in a more stable USB connection.
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*/
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setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
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setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
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setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
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/* Toggle USB power */
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ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
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if (ret < 0)
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return ret;
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gpio_direction_output(GPIO_USB0_PWR_ON, 0);
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ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
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if (ret < 0)
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return ret;
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gpio_direction_output(GPIO_USB1_PWR_ON, 0);
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mdelay(1);
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gpio_set_value(GPIO_USB0_PWR_ON, 1);
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gpio_set_value(GPIO_USB1_PWR_ON, 1);
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return 0;
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}
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int checkboard(void)
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{
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board_fpga_add();
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return 0;
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}
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#ifdef CONFIG_NET
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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#endif
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_LATE_INIT)
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int board_late_init(void)
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{
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pci_dev_t bdf;
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ulong bootcount;
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/*
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* Check if the PEX switch is detected (somtimes its not available
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* on the PCIe bus). In this case, try to recover by issuing a
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* soft-reset or even a power-cycle, depending on the bootcounter
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* value.
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*/
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bdf = pci_find_device(PCI_VENDOR_ID_PLX, 0x8619, 0);
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if (bdf == -1) {
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unsigned long start_time = get_timer(0);
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u8 i2c_buf[8];
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int ret;
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/* PEX switch not found! */
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bootcount = bootcount_load();
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printf("Failed to find PLX PEX-switch (bootcount=%ld)\n",
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bootcount);
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/*
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* The user can exit this boot-loop in the error case by
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* hitting Ctrl-C. So wait some time for this key here.
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*/
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printf("Continue booting with Ctrl-C, otherwise rebooting\n");
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do {
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/* Handle control-c and timeouts */
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if (ctrlc()) {
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printf("PEX error boot-loop aborted!\n");
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return 0;
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}
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} while (get_timer(start_time) < ABORT_TIMEOUT);
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/*
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* At this stage the bootcounter has not been incremented
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* yet. We need to do this manually here to get an actually
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* working bootcounter in this error case.
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*/
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bootcount_inc();
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if (bootcount > PEX_SWITCH_NOT_FOUNT_LIMIT) {
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printf("Issuing power-switch via uC!\n");
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printf("Issuing power-switch via uC!\n");
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i2c_set_bus_num(STM_I2C_BUS);
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i2c_buf[0] = STM_I2C_ADDR << 1;
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i2c_buf[1] = 0xc5; /* cmd */
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i2c_buf[2] = 0x01; /* enable */
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/* Delay before reboot */
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i2c_buf[3] = REBOOT_DELAY & 0x00ff;
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i2c_buf[4] = (REBOOT_DELAY & 0xff00) >> 8;
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/* Delay before shutdown */
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i2c_buf[5] = 0x00;
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i2c_buf[6] = 0x00;
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i2c_buf[7] = crc8(0x72, &i2c_buf[0], 7);
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ret = i2c_write(STM_I2C_ADDR, 0, 0, &i2c_buf[1], 7);
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if (ret) {
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printf("I2C write error (ret=%d)\n", ret);
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printf("Issuing soft-reset...\n");
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/* default handling: SOFT reset */
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do_reset(NULL, 0, 0, NULL);
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}
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/* Wait for power-cycle to occur... */
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printf("Waiting for power-cycle via uC...\n");
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while (1)
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;
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} else {
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printf("Issuing soft-reset...\n");
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/* default handling: SOFT reset */
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do_reset(NULL, 0, 0, NULL);
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}
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}
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI)
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int do_pcie_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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pci_dev_t bdf;
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u16 ven_id, dev_id;
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if (argc != 3)
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return cmd_usage(cmdtp);
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ven_id = simple_strtoul(argv[1], NULL, 16);
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dev_id = simple_strtoul(argv[2], NULL, 16);
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printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n",
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ven_id, dev_id);
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/*
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* Check if the PCIe device is detected (somtimes its not available
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* on the PCIe bus)
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*/
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bdf = pci_find_device(ven_id, dev_id, 0);
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if (bdf == -1) {
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/* PCIe device not found! */
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printf("Failed to find PCIe device\n");
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} else {
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/* PCIe device found! */
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printf("PCIe device found, resetting board...\n");
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/* default handling: SOFT reset */
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do_reset(NULL, 0, 0, NULL);
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}
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return 0;
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}
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U_BOOT_CMD(
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pcie, 3, 0, do_pcie_test,
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"Test for presence of a PCIe device",
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"<VendorID> <DeviceID>"
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);
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#endif
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