mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 07:06:19 +09:00
067716bac5
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
256 lines
7.6 KiB
C
256 lines
7.6 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the phytec PCM-052 SoM.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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#define CONFIG_VF610
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* Enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/* NAND support */
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_USE_ARCH_MEMCPY
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_JFFS2_NAND
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/* UBI */
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_LZO
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/* Dynamic MTD partition support */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_MTD_DEVICE
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#define MTDIDS_DEFAULT "nand0=NAND"
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#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\
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",384k(bootloader)"\
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",128k(env1)"\
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",128k(env2)"\
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",128k(dtb)"\
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",6144k(kernel)"\
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",65536k(ramdisk)"\
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",450944k(root)"
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#endif
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#define CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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/*#define CONFIG_ESDHC_DETECT_USE_EXTERN_IRQ1*/
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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/* QSPI Configs*/
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#ifdef CONFIG_FSL_QSPI
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#define CONFIG_SPI_FLASH
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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#define CONFIG_SYS_FSL_QSPI_LE
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#endif
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_I2C_MXC
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/* RTC (actually an RV-4162 but M41T62-compatible) */
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#define CONFIG_CMD_DATE
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#define CONFIG_RTC_M41T62
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_RTC_BUS_NUM 2
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/* EEPROM (24FC256) */
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#define CONFIG_CMD_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_I2C_EEPROM_BUS 2
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#define CONFIG_LOADADDR 0x82000000
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/* We boot from the gfxRAM area of the OCRAM. */
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#define CONFIG_SYS_TEXT_BASE 0x3f408000
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#define CONFIG_BOARD_SIZE_LIMIT 524288
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#define CONFIG_BOOTCOMMAND "run bootcmd_sd"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0xffffffff\0" \
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"initrd_high=0xffffffff\0" \
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"blimg_file=u-boot.imx\0" \
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"blsec_addr=0x81000000\0" \
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"blimg_addr=0x81000400\0" \
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"kernel_file=zImage\0" \
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"kernel_addr=0x82000000\0" \
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"fdt_file=vf610-pcm052.dtb\0" \
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"fdt_addr=0x81000000\0" \
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"ram_file=uRamdisk\0" \
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"ram_addr=0x83000000\0" \
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"filesys=rootfs.ubifs\0" \
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"sys_addr=0x81000000\0" \
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"tftploc=/path/to/tftp/directory/\0" \
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"nfs_root=/path/to/nfs/root\0" \
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"tftptimeout=1000\0" \
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"tftptimeoutcountmax=1000000\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"bootargs_base=setenv bootargs rw mem=256M " \
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"console=ttyLP1,115200n8\0" \
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"bootargs_sd=setenv bootargs ${bootargs} " \
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"root=/dev/mmcblk0p2 rootwait\0" \
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"bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \
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"nfsroot=${serverip}:${nfs_root},v3,tcp\0" \
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"bootargs_nand=setenv bootargs ${bootargs} " \
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"ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \
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"bootargs_ram=setenv bootargs ${bootargs} " \
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"root=/dev/ram rw initrd=${ram_addr}\0" \
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"bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \
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"fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \
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"fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \
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"bootz ${kernel_addr} - ${fdt_addr}\0" \
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"bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \
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"tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \
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"tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \
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"bootz ${kernel_addr} - ${fdt_addr}\0" \
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"bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \
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"nand read ${fdt_addr} dtb; " \
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"nand read ${kernel_addr} kernel; " \
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"bootz ${kernel_addr} - ${fdt_addr}\0" \
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"bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \
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"nand read ${fdt_addr} dtb; " \
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"nand read ${kernel_addr} kernel; " \
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"nand read ${ram_addr} ramdisk; " \
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"bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \
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"update_bootloader_from_tftp=mtdparts default; " \
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"nand read ${blsec_addr} bootloader; " \
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"mw.b ${blimg_addr} 0xff 0x5FC00; " \
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"if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \
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"nand erase.part bootloader; " \
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"nand write ${blsec_addr} bootloader ${filesize}; fi\0" \
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"update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \
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"${kernel_file}; " \
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"then mtdparts default; " \
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"nand erase.part kernel; " \
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"nand write ${kernel_addr} kernel ${filesize}; " \
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"if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \
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"nand erase.part dtb; " \
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"nand write ${fdt_addr} dtb ${filesize}; fi\0" \
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"update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \
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"then setenv fdtsize ${filesize}; " \
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"if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \
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"mtdparts default; " \
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"nand erase.part dtb; " \
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"nand write ${fdt_addr} dtb ${fdtsize}; " \
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"nand erase.part kernel; " \
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"nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \
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"update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \
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"then mtdparts default; " \
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"nand erase.part root; " \
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"ubi part root; " \
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"ubi create rootfs; " \
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"ubi write ${sys_addr} rootfs ${filesize}; fi\0" \
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"update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \
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"then mtdparts default; " \
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"nand erase.part ramdisk; " \
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"nand write ${ram_addr} ramdisk ${filesize}; fi\0"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE \
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(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x80010000
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#define CONFIG_SYS_MEMTEST_END 0x87C00000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/*
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* Stack sizes
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/* Physical memory map */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM (0x80000000)
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#define PHYS_SDRAM_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* FLASH and environment organization */
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#define CONFIG_SYS_NO_FLASH
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#ifdef CONFIG_ENV_IS_IN_MMC
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_OFFSET (12 * 64 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_OFFSET 0xA0000
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#define CONFIG_ENV_SIZE_REDUND (8 * 1024)
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#define CONFIG_ENV_OFFSET_REDUND 0xC0000
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#endif
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#endif
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