mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-14 08:43:22 +09:00
dd6df64c68
There are two issues:
(1) The spin table doesn't convert the endianness of the jump address.
Although there is code for it, the result isn't used at all (x0).
(2) If something goes wrong, the function returns. But that doesn't
make sense at all.
Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.
This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
119 lines
2.8 KiB
ArmAsm
119 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014-2015 Freescale Semiconductor
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* Copyright 2019 NXP
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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.align 3
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.global secondary_boot_addr
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secondary_boot_addr:
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.quad __secondary_boot_func
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.global secondary_boot_code_start
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secondary_boot_code_start:
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.quad __secondary_boot_code_start
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.global secondary_boot_code_size
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secondary_boot_code_size:
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.quad __secondary_boot_code_end - __secondary_boot_code_start
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/* Using 64 bit alignment since the spin table is accessed as data */
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.align 3
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/* Secondary Boot Code starts here */
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__secondary_boot_code_start:
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__spin_table:
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.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
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.align 2
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__secondary_boot_func:
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/*
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* MPIDR_EL1 Fields:
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* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
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* MPIDR[7:2] = AFF0_RES
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* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
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* MPIDR[23:16] = AFF2_CLUSTERID
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* MPIDR[24] = MT
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* MPIDR[29:25] = RES0
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* MPIDR[30] = U
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* MPIDR[31] = ME
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* MPIDR[39:32] = AFF3
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*
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* Linear Processor ID (LPID) calculation from MPIDR_EL1:
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* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
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* until AFF2_CLUSTERID and AFF3 have non-zero values)
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*
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* LPID = MPIDR[15:8] | MPIDR[1:0]
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*/
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mrs x0, mpidr_el1
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ubfm x1, x0, #8, #15
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ubfm x2, x0, #0, #1
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orr x10, x2, x1, lsl #2 /* x10 has LPID */
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ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
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/*
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* offset of the spin table element for this core from start of spin
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* table (each elem is padded to 64 bytes)
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*/
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lsl x1, x10, #6
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adr x0, __spin_table
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/* physical address of this cpus spin table element */
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add x11, x1, x0
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adr x0, __real_cntfrq
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ldr x0, [x0]
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msr cntfrq_el0, x0 /* set with real frequency */
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str x9, [x11, #16] /* LPID */
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mov x4, #1
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str x4, [x11, #8] /* STATUS */
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dsb sy
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1:
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wfe
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ldr x4, [x11]
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cbz x4, 1b
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mrs x1, sctlr_el2
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tbz x1, #25, 2f
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rev x4, x4 /* BE to LE conversion */
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2:
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ldr x6, =ES_TO_AARCH64
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x5, 3f
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switch_el x7, 0f, _dead_loop, _dead_loop
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0: armv8_switch_to_el2_m x5, x6, x7
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#endif
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3:
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ldr x7, [x11, #24] /* ARCH_COMP */
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cbz x7, 4f
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ldr x6, =ES_TO_AARCH32
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4:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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switch_el x7, _dead_loop, 0f, _dead_loop
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0: armv8_switch_to_el1_m x4, x6, x7
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#else
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switch_el x7, 0f, _dead_loop, _dead_loop
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0: armv8_switch_to_el2_m x4, x6, x7
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#endif
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_dead_loop:
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wfe
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b _dead_loop
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/* Ensure that the literals used by the secondary boot code are
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* assembled within it (this is required so that we can protect
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* this area with a single memreserve region
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*/
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.ltorg
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/* 64 bit alignment for elements accessed as data */
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.align 3
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.global __real_cntfrq
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__real_cntfrq:
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.quad COUNTER_FREQUENCY
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/* Secondary Boot Code ends here */
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__secondary_boot_code_end:
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