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https://github.com/brain-hackers/u-boot-brain
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![Stephen Warren](/assets/img/avatar_default.png)
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
225 lines
5.8 KiB
C
225 lines
5.8 KiB
C
/*
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* Qualcomm UART driver
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* UART will work in Data Mover mode.
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* Based on Linux driver.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <serial.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <linux/compiler.h>
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/* Serial registers - this driver works in uartdm mode*/
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#define UARTDM_DMRX 0x34 /* Max RX transfer length */
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#define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
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#define UARTDM_RXFS 0x50 /* RX channel status register */
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#define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
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#define UARTDM_RXFS_BUF_MASK 0x7
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#define UARTDM_SR 0xA4 /* Status register */
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#define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
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#define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
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#define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
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#define UARTDM_CR 0xA8 /* Command register */
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#define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
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#define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
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#define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
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#define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
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#define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
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#define UARTDM_IMR 0xB0 /* Interrupt mask register */
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#define UARTDM_ISR 0xB4 /* Interrupt status register */
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#define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
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#define UARTDM_TF 0x100 /* UART Transmit FIFO register */
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#define UARTDM_RF 0x140 /* UART Receive FIFO register */
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DECLARE_GLOBAL_DATA_PTR;
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struct msm_serial_data {
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phys_addr_t base;
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unsigned chars_cnt; /* number of buffered chars */
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uint32_t chars_buf; /* buffered chars */
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};
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static int msm_serial_fetch(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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unsigned sr;
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if (priv->chars_cnt)
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return priv->chars_cnt;
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/* Clear error in case of buffer overrun */
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if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
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writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
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/* We need to fetch new character */
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sr = readl(priv->base + UARTDM_SR);
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if (sr & UARTDM_SR_RX_READY) {
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/* There are at least 4 bytes in fifo */
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priv->chars_buf = readl(priv->base + UARTDM_RF);
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priv->chars_cnt = 4;
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} else {
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/* Check if there is anything in fifo */
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priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
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/* Extract number of characters in UART packing buffer*/
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priv->chars_cnt = (priv->chars_cnt >>
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UARTDM_RXFS_BUF_SHIFT) &
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UARTDM_RXFS_BUF_MASK;
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if (!priv->chars_cnt)
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return 0;
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/* There is at least one charcter, move it to fifo */
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writel(UARTDM_CR_CMD_FORCE_STALE,
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priv->base + UARTDM_CR);
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priv->chars_buf = readl(priv->base + UARTDM_RF);
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writel(UARTDM_CR_CMD_RESET_STALE_INT,
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priv->base + UARTDM_CR);
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writel(0x7, priv->base + UARTDM_DMRX);
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}
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return priv->chars_cnt;
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}
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static int msm_serial_getc(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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char c;
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if (!msm_serial_fetch(dev))
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return -EAGAIN;
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c = priv->chars_buf & 0xFF;
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priv->chars_buf >>= 8;
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priv->chars_cnt--;
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return c;
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}
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static int msm_serial_putc(struct udevice *dev, const char ch)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
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!(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
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return -EAGAIN;
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writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
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writel(1, priv->base + UARTDM_NCF_TX);
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writel(ch, priv->base + UARTDM_TF);
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return 0;
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}
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static int msm_serial_pending(struct udevice *dev, bool input)
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{
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if (input) {
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if (msm_serial_fetch(dev))
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return 1;
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}
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return 0;
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}
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static const struct dm_serial_ops msm_serial_ops = {
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.putc = msm_serial_putc,
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.pending = msm_serial_pending,
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.getc = msm_serial_getc,
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};
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static int msm_uart_clk_init(struct udevice *dev)
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{
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uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
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"clock-frequency", 115200);
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uint clkd[2]; /* clk_id and clk_no */
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int clk_offset;
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struct udevice *clk_dev;
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struct clk clk;
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int ret;
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ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
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2);
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if (ret)
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return ret;
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clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
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if (clk_offset < 0)
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return clk_offset;
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
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if (ret)
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return ret;
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clk.id = clkd[1];
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ret = clk_request(clk_dev, &clk);
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if (ret < 0)
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return ret;
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ret = clk_set_rate(&clk, clk_rate);
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clk_free(&clk);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int msm_serial_probe(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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msm_uart_clk_init(dev); /* Ignore return value and hope clock was
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properly initialized by earlier loaders */
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if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
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writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
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writel(0, priv->base + UARTDM_IMR);
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writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
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msm_serial_fetch(dev);
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return 0;
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}
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static int msm_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct msm_serial_data *priv = dev_get_priv(dev);
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priv->base = dev_get_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct udevice_id msm_serial_ids[] = {
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{ .compatible = "qcom,msm-uartdm-v1.4" },
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{ }
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};
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U_BOOT_DRIVER(serial_msm) = {
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.name = "serial_msm",
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.id = UCLASS_SERIAL,
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.of_match = msm_serial_ids,
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.ofdata_to_platdata = msm_serial_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct msm_serial_data),
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.probe = msm_serial_probe,
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.ops = &msm_serial_ops,
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};
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