mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 23:48:52 +09:00
![Stephen Warren](/assets/img/avatar_default.png)
In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
31 lines
1.1 KiB
Plaintext
31 lines
1.1 KiB
Plaintext
menu "Reset Controller Support"
|
|
|
|
config DM_RESET
|
|
bool "Enable reset controllers using Driver Model"
|
|
depends on DM && OF_CONTROL
|
|
help
|
|
Enable support for the reset controller driver class. Many hardware
|
|
modules are equipped with a reset signal, typically driven by some
|
|
reset controller hardware module within the chip. In U-Boot, reset
|
|
controller drivers allow control over these reset signals. In some
|
|
cases this API is applicable to chips outside the CPU as well,
|
|
although driving such reset isgnals using GPIOs may be more
|
|
appropriate in this case.
|
|
|
|
config SANDBOX_RESET
|
|
bool "Enable the sandbox reset test driver"
|
|
depends on DM_MAILBOX && SANDBOX
|
|
help
|
|
Enable support for a test reset controller implementation, which
|
|
simply accepts requests to reset various HW modules without actually
|
|
doing anything beyond a little error checking.
|
|
|
|
config TEGRA186_RESET
|
|
bool "Enable Tegra186 BPMP-based reset driver"
|
|
depends on TEGRA186_BPMP
|
|
help
|
|
Enable support for manipulating Tegra's on-SoC reset signals via IPC
|
|
requests to the BPMP (Boot and Power Management Processor).
|
|
|
|
endmenu
|