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![Wenyou Yang](/assets/img/avatar_default.png)
AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
183 lines
4.3 KiB
C
183 lines
4.3 KiB
C
/*
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* Atmel PIO4 pinctrl driver
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*
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* Copyright (C) 2016 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm/device.h>
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#include <dm/pinctrl.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach/atmel_pio4.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Warning:
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* In order to not introduce confusion between Atmel PIO groups and pinctrl
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* framework groups, Atmel PIO groups will be called banks.
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*/
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struct atmel_pio4_platdata {
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struct atmel_pio4_port *reg_base;
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};
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static const struct pinconf_param conf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
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{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
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{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
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{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
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};
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static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
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{
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const struct pinconf_param *params;
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u32 param, arg, conf = 0;
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u32 i;
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for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
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params = &conf_params[i];
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if (!fdt_get_property(blob, node, params->property, NULL))
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continue;
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param = params->param;
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arg = params->default_value;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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conf &= (~ATMEL_PIO_PUEN_MASK);
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conf &= (~ATMEL_PIO_PDEN_MASK);
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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conf |= ATMEL_PIO_PUEN_MASK;
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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conf |= ATMEL_PIO_PDEN_MASK;
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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if (arg == 0)
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conf &= (~ATMEL_PIO_OPD_MASK);
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else
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conf |= ATMEL_PIO_OPD_MASK;
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break;
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case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
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if (arg == 0)
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conf |= ATMEL_PIO_SCHMITT_MASK;
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else
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conf &= (~ATMEL_PIO_SCHMITT_MASK);
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break;
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case PIN_CONFIG_INPUT_DEBOUNCE:
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if (arg == 0) {
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conf &= (~ATMEL_PIO_IFEN_MASK);
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conf &= (~ATMEL_PIO_IFSCEN_MASK);
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} else {
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conf |= ATMEL_PIO_IFEN_MASK;
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conf |= ATMEL_PIO_IFSCEN_MASK;
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}
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break;
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default:
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printf("%s: Unsupported configuration parameter: %u\n",
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__func__, param);
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break;
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}
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}
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return conf;
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}
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static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
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u32 bank)
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{
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struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
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struct atmel_pio4_port *bank_base =
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(struct atmel_pio4_port *)((u32)plat->reg_base +
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ATMEL_PIO_BANK_OFFSET * bank);
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return bank_base;
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}
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#define MAX_PINMUX_ENTRIES 40
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static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct atmel_pio4_port *bank_base;
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const void *blob = gd->fdt_blob;
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int node = config->of_offset;
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u32 offset, func, bank, line;
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u32 cells[MAX_PINMUX_ENTRIES];
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u32 i, conf;
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int count;
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conf = atmel_pinctrl_get_pinconf(blob, node);
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count = fdtdec_get_int_array_count(blob, node, "pinmux",
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cells, ARRAY_SIZE(cells));
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if (count < 0) {
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printf("%s: bad pinmux array %d\n", __func__, count);
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return -EINVAL;
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}
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if (count > MAX_PINMUX_ENTRIES) {
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printf("%s: unsupported pinmux array count %d\n",
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__func__, count);
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return -EINVAL;
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}
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for (i = 0 ; i < count; i++) {
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offset = ATMEL_GET_PIN_NO(cells[i]);
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func = ATMEL_GET_PIN_FUNC(cells[i]);
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bank = ATMEL_PIO_BANK(offset);
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line = ATMEL_PIO_LINE(offset);
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bank_base = atmel_pio4_bank_base(dev, bank);
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writel(BIT(line), &bank_base->mskr);
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conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
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conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
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writel(conf, &bank_base->cfgr);
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}
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return 0;
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}
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const struct pinctrl_ops atmel_pinctrl_ops = {
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.set_state = atmel_pinctrl_set_state,
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};
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static int atmel_pinctrl_probe(struct udevice *dev)
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{
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struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
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fdt_addr_t addr_base;
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dev = dev_get_parent(dev);
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addr_base = dev_get_addr(dev);
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if (addr_base == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->reg_base = (struct atmel_pio4_port *)addr_base;
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return 0;
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}
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static const struct udevice_id atmel_pinctrl_match[] = {
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{ .compatible = "atmel,sama5d2-pinctrl" },
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{}
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};
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U_BOOT_DRIVER(atmel_pinctrl) = {
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.name = "pinctrl_atmel_pio4",
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.id = UCLASS_PINCTRL,
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.of_match = atmel_pinctrl_match,
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.probe = atmel_pinctrl_probe,
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.platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
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.ops = &atmel_pinctrl_ops,
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};
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