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![Stephen Warren](/assets/img/avatar_default.png)
Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
43 lines
1.5 KiB
Plaintext
43 lines
1.5 KiB
Plaintext
menu "PCI"
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config DM_PCI
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bool "Enable driver mode for PCI"
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depends on DM
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help
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Use driver model for PCI. Driver model is the new method for
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orgnising devices in U-Boot. For PCI, driver model keeps track of
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available PCI devices, allows scanning of PCI buses and provides
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device configuration support.
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config DM_PCI_COMPAT
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bool "Enable compatible functions for PCI"
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depends on DM_PCI
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help
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Enable compatibility functions for PCI so that old code can be used
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with CONFIG_DM_PCI enabled. This should be used as an interim
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measure when porting a board to use driver model for PCI. Once the
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board is fully supported, this option should be disabled.
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config PCI_SANDBOX
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bool "Sandbox PCI support"
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depends on SANDBOX && DM_PCI
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help
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Support PCI on sandbox, as an emulated bus. This permits testing of
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PCI feature such as bus scanning, device configuration and device
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access. The available (emulated) devices are defined statically in
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the device tree but the normal PCI scan technique is used to find
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then.
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config PCI_TEGRA
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bool "Tegra PCI support"
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depends on TEGRA
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depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
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help
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Enable support for the PCIe controller found on some generations of
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Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
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3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
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with a total of 5 lanes. Some boards require this for Ethernet
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support to work (e.g. beaver, jetson-tk1).
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endmenu
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