mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
4c94aacd62
Unfortunately, the integrated macphy default is enabled, which will increase power consuming, if we do not use this PHY. So let's disable it at first, which will save power consuming. If we really use it, then enable it in driver level. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
552 lines
11 KiB
C
552 lines
11 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK322X_H
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#define _ASM_ARCH_GRF_RK322X_H
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#include <common.h>
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struct rk322x_grf {
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unsigned int gpio0a_iomux;
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unsigned int gpio0b_iomux;
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unsigned int gpio0c_iomux;
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unsigned int gpio0d_iomux;
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unsigned int gpio1a_iomux;
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unsigned int gpio1b_iomux;
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unsigned int gpio1c_iomux;
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unsigned int gpio1d_iomux;
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unsigned int gpio2a_iomux;
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unsigned int gpio2b_iomux;
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unsigned int gpio2c_iomux;
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unsigned int gpio2d_iomux;
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unsigned int gpio3a_iomux;
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unsigned int gpio3b_iomux;
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unsigned int gpio3c_iomux;
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unsigned int gpio3d_iomux;
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unsigned int reserved1[4];
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unsigned int con_iomux;
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unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
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unsigned int gpio0_p[4];
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unsigned int gpio1_p[4];
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unsigned int gpio2_p[4];
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unsigned int gpio3_p[4];
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unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
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unsigned int gpio0_e[4];
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unsigned int gpio1_e[4];
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unsigned int gpio2_e[4];
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unsigned int gpio3_e[4];
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unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
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unsigned int soc_con[7];
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unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
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unsigned int soc_status[3];
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unsigned int chip_id;
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unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
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unsigned int cpu_con[4];
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unsigned int reserved7[4];
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unsigned int cpu_status[2];
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unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
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unsigned int os_reg[8];
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unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
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unsigned int ddrc_stat;
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unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
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unsigned int sig_detect_con[2];
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unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
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unsigned int sig_detect_status[2];
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unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
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unsigned int sig_detect_clr[2];
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unsigned int reserved13[(0x6b0 - 0x6a4) / 4 - 1];
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unsigned int emmc_det;
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unsigned int reserved14[(0x700 - 0x6b0) / 4 - 1];
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unsigned int host0_con[3];
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unsigned int reserved15;
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unsigned int host1_con[3];
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unsigned int reserved16;
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unsigned int host2_con[3];
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unsigned int reserved17[(0x760 - 0x728) / 4 - 1];
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unsigned int usbphy0_con[27];
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unsigned int reserved18[(0x800 - 0x7c8) / 4 - 1];
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unsigned int usbphy1_con[27];
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unsigned int reserved19[(0x880 - 0x868) / 4 - 1];
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unsigned int otg_con0;
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unsigned int uoc_status0;
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unsigned int reserved20[(0x900 - 0x884) / 4 - 1];
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unsigned int mac_con[2];
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unsigned int reserved21[(0xb00 - 0x904) / 4 - 1];
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unsigned int macphy_con[4];
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unsigned int macphy_status;
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};
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check_member(rk322x_grf, ddrc_stat, 0x604);
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struct rk322x_sgrf {
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unsigned int soc_con[11];
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unsigned int busdmac_con[4];
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};
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/* GRF_GPIO0A_IOMUX */
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enum {
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GPIO0A7_SHIFT = 14,
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GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
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GPIO0A7_GPIO = 0,
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GPIO0A7_I2C3_SDA,
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GPIO0A7_HDMI_DDCSDA,
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GPIO0A6_SHIFT = 12,
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GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
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GPIO0A6_GPIO = 0,
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GPIO0A6_I2C3_SCL,
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GPIO0A6_HDMI_DDCSCL,
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GPIO0A3_SHIFT = 6,
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GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
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GPIO0A3_GPIO = 0,
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GPIO0A3_I2C1_SDA,
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GPIO0A3_SDIO_CMD,
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GPIO0A2_SHIFT = 4,
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GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
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GPIO0A2_GPIO = 0,
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GPIO0A2_I2C1_SCL,
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GPIO0A1_SHIFT = 2,
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GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
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GPIO0A1_GPIO = 0,
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GPIO0A1_I2C0_SDA,
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GPIO0A0_SHIFT = 0,
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GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
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GPIO0A0_GPIO = 0,
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GPIO0A0_I2C0_SCL,
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};
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/* GRF_GPIO0B_IOMUX */
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enum {
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GPIO0B7_SHIFT = 14,
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GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
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GPIO0B7_GPIO = 0,
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GPIO0B7_HDMI_HDP,
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GPIO0B6_SHIFT = 12,
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GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
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GPIO0B6_GPIO = 0,
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GPIO0B6_I2S_SDI,
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GPIO0B6_SPI_CSN0,
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GPIO0B5_SHIFT = 10,
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GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
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GPIO0B5_GPIO = 0,
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GPIO0B5_I2S_SDO,
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GPIO0B5_SPI_RXD,
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GPIO0B3_SHIFT = 6,
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GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
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GPIO0B3_GPIO = 0,
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GPIO0B3_I2S1_LRCKRX,
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GPIO0B3_SPI_TXD,
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GPIO0B1_SHIFT = 2,
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GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
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GPIO0B1_GPIO = 0,
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GPIO0B1_I2S_SCLK,
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GPIO0B1_SPI_CLK,
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GPIO0B0_SHIFT = 0,
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GPIO0B0_MASK = 3,
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GPIO0B0_GPIO = 0,
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GPIO0B0_I2S_MCLK,
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};
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/* GRF_GPIO0C_IOMUX */
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enum {
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GPIO0C4_SHIFT = 8,
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GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
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GPIO0C4_GPIO = 0,
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GPIO0C4_HDMI_CECSDA,
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GPIO0C1_SHIFT = 2,
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GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
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GPIO0C1_GPIO = 0,
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GPIO0C1_UART0_RSTN,
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GPIO0C1_CLK_OUT1,
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};
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/* GRF_GPIO0D_IOMUX */
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enum {
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GPIO0D6_SHIFT = 12,
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GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
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GPIO0D6_GPIO = 0,
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GPIO0D6_SDIO_PWREN,
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GPIO0D6_PWM11,
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GPIO0D4_SHIFT = 8,
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GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
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GPIO0D4_GPIO = 0,
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GPIO0D4_PWM2,
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GPIO0D3_SHIFT = 6,
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GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
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GPIO0D3_GPIO = 0,
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GPIO0D3_PWM1,
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GPIO0D2_SHIFT = 4,
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GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
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GPIO0D2_GPIO = 0,
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GPIO0D2_PWM0,
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};
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/* GRF_GPIO1A_IOMUX */
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enum {
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GPIO1A7_SHIFT = 14,
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GPIO1A7_MASK = 1,
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GPIO1A7_GPIO = 0,
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GPIO1A7_SDMMC_WRPRT,
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};
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/* GRF_GPIO1B_IOMUX */
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enum {
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GPIO1B7_SHIFT = 14,
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GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
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GPIO1B7_GPIO = 0,
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GPIO1B7_SDMMC_CMD,
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GPIO1B6_SHIFT = 12,
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GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
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GPIO1B6_GPIO = 0,
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GPIO1B6_SDMMC_PWREN,
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GPIO1B4_SHIFT = 8,
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GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
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GPIO1B4_GPIO = 0,
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GPIO1B4_SPI_CSN1,
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GPIO1B4_PWM12,
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GPIO1B3_SHIFT = 6,
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GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
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GPIO1B3_GPIO = 0,
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GPIO1B3_UART1_RSTN,
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GPIO1B3_PWM13,
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GPIO1B2_SHIFT = 4,
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GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
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GPIO1B2_GPIO = 0,
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GPIO1B2_UART1_SIN,
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GPIO1B2_UART21_SIN,
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART1_SOUT,
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GPIO1B1_UART21_SOUT,
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};
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/* GRF_GPIO1C_IOMUX */
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enum {
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GPIO1C7_SHIFT = 14,
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GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
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GPIO1C7_GPIO = 0,
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GPIO1C7_NAND_CS3,
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GPIO1C7_EMMC_RSTNOUT,
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GPIO1C6_SHIFT = 12,
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GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
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GPIO1C6_GPIO = 0,
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GPIO1C6_NAND_CS2,
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GPIO1C6_EMMC_CMD,
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GPIO1C5_SHIFT = 10,
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GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
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GPIO1C5_GPIO = 0,
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GPIO1C5_SDMMC_D3,
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GPIO1C5_JTAG_TMS,
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GPIO1C4_SHIFT = 8,
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GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
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GPIO1C4_GPIO = 0,
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GPIO1C4_SDMMC_D2,
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GPIO1C4_JTAG_TCK,
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GPIO1C3_SHIFT = 6,
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GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
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GPIO1C3_GPIO = 0,
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GPIO1C3_SDMMC_D1,
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GPIO1C3_UART2_SIN,
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GPIO1C2_SHIFT = 4,
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GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
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GPIO1C2_GPIO = 0,
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GPIO1C2_SDMMC_D0,
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GPIO1C2_UART2_SOUT,
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GPIO1C1_SHIFT = 2,
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GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
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GPIO1C1_GPIO = 0,
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GPIO1C1_SDMMC_DETN,
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GPIO1C0_SHIFT = 0,
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GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
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GPIO1C0_GPIO = 0,
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GPIO1C0_SDMMC_CLKOUT,
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};
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/* GRF_GPIO1D_IOMUX */
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enum {
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GPIO1D7_SHIFT = 14,
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GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
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GPIO1D7_GPIO = 0,
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GPIO1D7_NAND_D7,
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GPIO1D7_EMMC_D7,
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GPIO1D6_SHIFT = 12,
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GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
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GPIO1D6_GPIO = 0,
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GPIO1D6_NAND_D6,
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GPIO1D6_EMMC_D6,
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GPIO1D5_SHIFT = 10,
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GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
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GPIO1D5_GPIO = 0,
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GPIO1D5_NAND_D5,
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GPIO1D5_EMMC_D5,
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GPIO1D4_SHIFT = 8,
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GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
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GPIO1D4_GPIO = 0,
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GPIO1D4_NAND_D4,
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GPIO1D4_EMMC_D4,
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GPIO1D3_SHIFT = 6,
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GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
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GPIO1D3_GPIO = 0,
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GPIO1D3_NAND_D3,
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GPIO1D3_EMMC_D3,
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GPIO1D2_SHIFT = 4,
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GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
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GPIO1D2_GPIO = 0,
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GPIO1D2_NAND_D2,
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GPIO1D2_EMMC_D2,
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GPIO1D1_SHIFT = 2,
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GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
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GPIO1D1_GPIO = 0,
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GPIO1D1_NAND_D1,
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GPIO1D1_EMMC_D1,
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GPIO1D0_SHIFT = 0,
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GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
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GPIO1D0_GPIO = 0,
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GPIO1D0_NAND_D0,
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GPIO1D0_EMMC_D0,
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};
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/* GRF_GPIO2A_IOMUX */
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enum {
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GPIO2A7_SHIFT = 14,
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GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
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GPIO2A7_GPIO = 0,
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GPIO2A7_NAND_DQS,
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GPIO2A7_EMMC_CLKOUT,
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GPIO2A5_SHIFT = 10,
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GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
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GPIO2A5_GPIO = 0,
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GPIO2A5_NAND_WP,
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GPIO2A5_EMMC_PWREN,
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GPIO2A4_SHIFT = 8,
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GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
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GPIO2A4_GPIO = 0,
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GPIO2A4_NAND_RDY,
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GPIO2A4_EMMC_CMD,
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GPIO2A3_SHIFT = 6,
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GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
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GPIO2A3_GPIO = 0,
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GPIO2A3_NAND_RDN,
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GPIO2A4_SPI1_CSN1,
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GPIO2A2_SHIFT = 4,
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GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
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GPIO2A2_GPIO = 0,
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GPIO2A2_NAND_WRN,
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GPIO2A4_SPI1_CSN0,
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GPIO2A1_SHIFT = 2,
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GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
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GPIO2A1_GPIO = 0,
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GPIO2A1_NAND_CLE,
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GPIO2A1_SPI1_TXD,
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GPIO2A0_SHIFT = 0,
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GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
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GPIO2A0_GPIO = 0,
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GPIO2A0_NAND_ALE,
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GPIO2A0_SPI1_RXD,
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};
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/* GRF_GPIO2B_IOMUX */
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enum {
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GPIO2B7_SHIFT = 14,
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GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
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GPIO2B7_GPIO = 0,
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GPIO2B7_GMAC_RXER,
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GPIO2B6_SHIFT = 12,
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GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
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GPIO2B6_GPIO = 0,
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GPIO2B6_GMAC_CLK,
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GPIO2B6_MAC_LINK,
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GPIO2B5_SHIFT = 10,
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GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
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GPIO2B5_GPIO = 0,
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GPIO2B5_GMAC_TXEN,
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GPIO2B4_SHIFT = 8,
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GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
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GPIO2B4_GPIO = 0,
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GPIO2B4_GMAC_MDIO,
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GPIO2B3_SHIFT = 6,
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GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
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GPIO2B3_GPIO = 0,
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GPIO2B3_GMAC_RXCLK,
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GPIO2B2_SHIFT = 4,
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GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
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GPIO2B2_GPIO = 0,
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GPIO2B2_GMAC_CRS,
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GPIO2B1_SHIFT = 2,
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GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
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GPIO2B1_GPIO = 0,
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GPIO2B1_GMAC_TXCLK,
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GPIO2B0_SHIFT = 0,
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GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
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GPIO2B0_GPIO = 0,
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GPIO2B0_GMAC_RXDV,
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GPIO2B0_MAC_SPEED_IOUT,
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};
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/* GRF_GPIO2C_IOMUX */
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enum {
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GPIO2C7_SHIFT = 14,
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GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
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GPIO2C7_GPIO = 0,
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GPIO2C7_GMAC_TXD3,
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GPIO2C6_SHIFT = 12,
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GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
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GPIO2C6_GPIO = 0,
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GPIO2C6_GMAC_TXD2,
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GPIO2C5_SHIFT = 10,
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GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
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GPIO2C5_GPIO = 0,
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GPIO2C5_I2C2_SCL,
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GPIO2C5_GMAC_RXD2,
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GPIO2C4_SHIFT = 8,
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GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
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GPIO2C4_GPIO = 0,
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GPIO2C4_I2C2_SDA,
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GPIO2C4_GMAC_RXD3,
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GPIO2C3_SHIFT = 6,
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GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
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GPIO2C3_GPIO = 0,
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GPIO2C3_GMAC_TXD0,
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GPIO2C2_SHIFT = 4,
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GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
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GPIO2C2_GPIO = 0,
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GPIO2C2_GMAC_TXD1,
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GPIO2C1_SHIFT = 2,
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GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
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GPIO2C1_GPIO = 0,
|
|
GPIO2C1_GMAC_RXD0,
|
|
|
|
GPIO2C0_SHIFT = 0,
|
|
GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
|
|
GPIO2C0_GPIO = 0,
|
|
GPIO2C0_GMAC_RXD1,
|
|
};
|
|
|
|
/* GRF_GPIO2D_IOMUX */
|
|
enum {
|
|
GPIO2D1_SHIFT = 2,
|
|
GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
|
|
GPIO2D1_GPIO = 0,
|
|
GPIO2D1_GMAC_MDC,
|
|
|
|
GPIO2D0_SHIFT = 0,
|
|
GPIO2D0_MASK = 3,
|
|
GPIO2D0_GPIO = 0,
|
|
GPIO2D0_GMAC_COL,
|
|
};
|
|
|
|
/* GRF_GPIO3C_IOMUX */
|
|
enum {
|
|
GPIO3C6_SHIFT = 12,
|
|
GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
|
|
GPIO3C6_GPIO = 0,
|
|
GPIO3C6_DRV_VBUS1,
|
|
|
|
GPIO3C5_SHIFT = 10,
|
|
GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
|
|
GPIO3C5_GPIO = 0,
|
|
GPIO3C5_PWM10,
|
|
|
|
GPIO3C1_SHIFT = 2,
|
|
GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
|
|
GPIO3C1_GPIO = 0,
|
|
GPIO3C1_DRV_VBUS,
|
|
};
|
|
|
|
/* GRF_GPIO3D_IOMUX */
|
|
enum {
|
|
GPIO3D2_SHIFT = 4,
|
|
GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
|
|
GPIO3D2_GPIO = 0,
|
|
GPIO3D2_PWM3,
|
|
};
|
|
|
|
/* GRF_CON_IOMUX */
|
|
enum {
|
|
CON_IOMUX_GMAC_SHIFT = 15,
|
|
CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
|
|
CON_IOMUX_UART1SEL_SHIFT = 11,
|
|
CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
|
|
CON_IOMUX_UART2SEL_SHIFT = 8,
|
|
CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
|
|
CON_IOMUX_UART2SEL_2 = 0,
|
|
CON_IOMUX_UART2SEL_21,
|
|
CON_IOMUX_EMMCSEL_SHIFT = 7,
|
|
CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
|
|
CON_IOMUX_PWM3SEL_SHIFT = 3,
|
|
CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
|
|
CON_IOMUX_PWM2SEL_SHIFT = 2,
|
|
CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
|
|
CON_IOMUX_PWM1SEL_SHIFT = 1,
|
|
CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
|
|
CON_IOMUX_PWM0SEL_SHIFT = 0,
|
|
CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
|
|
};
|
|
|
|
/* GRF_MACPHY_CON0 */
|
|
enum {
|
|
MACPHY_CFG_ENABLE_SHIFT = 0,
|
|
MACPHY_CFG_ENABLE_MASK = 1 << MACPHY_CFG_ENABLE_SHIFT,
|
|
};
|
|
#endif
|