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![Simon Glass](/assets/img/avatar_default.png)
These functions really don't belong in physmem as they relate to the cpu. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
/*
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* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*/
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#include <common.h>
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#include <physmem.h>
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#include <asm/cpu.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Large pages are 2MB. */
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#define LARGE_PAGE_SIZE ((1 << 20) * 2)
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/*
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* Paging data structures.
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*/
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struct pdpe {
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uint64_t p:1;
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uint64_t mbz_0:2;
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uint64_t pwt:1;
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uint64_t pcd:1;
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uint64_t mbz_1:4;
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uint64_t avl:3;
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uint64_t base:40;
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uint64_t mbz_2:12;
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};
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typedef struct pdpe pdpt_t[512];
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struct pde {
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uint64_t p:1; /* present */
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uint64_t rw:1; /* read/write */
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uint64_t us:1; /* user/supervisor */
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uint64_t pwt:1; /* page-level writethrough */
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uint64_t pcd:1; /* page-level cache disable */
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uint64_t a:1; /* accessed */
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uint64_t d:1; /* dirty */
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uint64_t ps:1; /* page size */
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uint64_t g:1; /* global page */
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uint64_t avl:3; /* available to software */
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uint64_t pat:1; /* page-attribute table */
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uint64_t mbz_0:8; /* must be zero */
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uint64_t base:31; /* base address */
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};
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typedef struct pde pdt_t[512];
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static pdpt_t pdpt __aligned(4096);
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static pdt_t pdts[4] __aligned(4096);
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/*
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* Map a virtual address to a physical address and optionally invalidate any
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* old mapping.
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*
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* @param virt The virtual address to use.
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* @param phys The physical address to use.
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* @param invlpg Whether to use invlpg to clear any old mappings.
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*/
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static void x86_phys_map_page(uintptr_t virt, phys_addr_t phys, int invlpg)
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{
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/* Extract the two bit PDPT index and the 9 bit PDT index. */
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uintptr_t pdpt_idx = (virt >> 30) & 0x3;
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uintptr_t pdt_idx = (virt >> 21) & 0x1ff;
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/* Set up a handy pointer to the appropriate PDE. */
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struct pde *pde = &(pdts[pdpt_idx][pdt_idx]);
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memset(pde, 0, sizeof(struct pde));
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pde->p = 1;
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pde->rw = 1;
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pde->us = 1;
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pde->ps = 1;
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pde->base = phys >> 21;
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if (invlpg) {
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/* Flush any stale mapping out of the TLBs. */
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__asm__ __volatile__(
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"invlpg %0\n\t"
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:
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: "m" (*(uint8_t *)virt)
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);
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}
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}
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/* Identity map the lower 4GB and turn on paging with PAE. */
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static void x86_phys_enter_paging(void)
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{
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phys_addr_t page_addr;
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unsigned i;
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/* Zero out the page tables. */
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memset(pdpt, 0, sizeof(pdpt));
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memset(pdts, 0, sizeof(pdts));
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/* Set up the PDPT. */
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for (i = 0; i < ARRAY_SIZE(pdts); i++) {
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pdpt[i].p = 1;
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pdpt[i].base = ((uintptr_t)&pdts[i]) >> 12;
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}
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/* Identity map everything up to 4GB. */
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for (page_addr = 0; page_addr < (1ULL << 32);
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page_addr += LARGE_PAGE_SIZE) {
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/* There's no reason to invalidate the TLB with paging off. */
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x86_phys_map_page(page_addr, page_addr, 0);
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}
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cpu_enable_paging_pae((ulong)pdpt);
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}
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/* Disable paging and PAE mode. */
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static void x86_phys_exit_paging(void)
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{
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cpu_disable_paging_pae();
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}
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/*
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* Set physical memory to a particular value when the whole region fits on one
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* page.
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*
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* @param map_addr The address that starts the physical page.
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* @param offset How far into that page to start setting a value.
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* @param c The value to set memory to.
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* @param size The size in bytes of the area to set.
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*/
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static void x86_phys_memset_page(phys_addr_t map_addr, uintptr_t offset, int c,
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unsigned size)
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{
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/*
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* U-Boot should be far away from the beginning of memory, so that's a
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* good place to map our window on top of.
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*/
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const uintptr_t window = LARGE_PAGE_SIZE;
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/* Make sure the window is below U-Boot. */
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assert(window + LARGE_PAGE_SIZE <
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gd->relocaddr - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_STACK_SIZE);
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/* Map the page into the window and then memset the appropriate part. */
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x86_phys_map_page(window, map_addr, 1);
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memset((void *)(window + offset), c, size);
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}
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/*
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* A physical memory anologue to memset with matching parameters and return
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* value.
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*/
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phys_addr_t arch_phys_memset(phys_addr_t start, int c, phys_size_t size)
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{
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const phys_addr_t max_addr = (phys_addr_t)~(uintptr_t)0;
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const phys_addr_t orig_start = start;
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if (!size)
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return orig_start;
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/* Handle memory below 4GB. */
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if (start <= max_addr) {
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phys_size_t low_size = min(max_addr + 1 - start, size);
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void *start_ptr = (void *)(uintptr_t)start;
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assert(((phys_addr_t)(uintptr_t)start) == start);
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memset(start_ptr, c, low_size);
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start += low_size;
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size -= low_size;
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}
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/* Use paging and PAE to handle memory above 4GB up to 64GB. */
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if (size) {
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phys_addr_t map_addr = start & ~(LARGE_PAGE_SIZE - 1);
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phys_addr_t offset = start - map_addr;
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x86_phys_enter_paging();
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/* Handle the first partial page. */
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if (offset) {
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phys_addr_t end =
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min(map_addr + LARGE_PAGE_SIZE, start + size);
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phys_size_t cur_size = end - start;
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x86_phys_memset_page(map_addr, offset, c, cur_size);
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size -= cur_size;
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map_addr += LARGE_PAGE_SIZE;
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}
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/* Handle the complete pages. */
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while (size > LARGE_PAGE_SIZE) {
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x86_phys_memset_page(map_addr, 0, c, LARGE_PAGE_SIZE);
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size -= LARGE_PAGE_SIZE;
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map_addr += LARGE_PAGE_SIZE;
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}
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/* Handle the last partial page. */
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if (size)
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x86_phys_memset_page(map_addr, 0, c, size);
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x86_phys_exit_paging();
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}
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return orig_start;
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}
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