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https://github.com/brain-hackers/u-boot-brain
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![Stefano Babic](/assets/img/avatar_default.png)
Each i.MX has its own gpio.h, defining the same structure. The internal GPIO controller has the same layout (at least for the register used by u-boot) and can be shared. Signed-off-by: Stefano Babic <sbabic@denx.de> Tested-by: Matt Sealey <matt@genesi-usa.com>
187 lines
5.9 KiB
C
187 lines
5.9 KiB
C
/*
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* (c) 2011 Graf-Syteco, Matthias Weisser
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* <weisserm@arcor.de>
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*
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* Based on tx25.c:
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on imx27lite.c:
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* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
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* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
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* And:
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* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx25-pinmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init()
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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struct iomuxc_pad_input_select *inputselect;
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u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
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u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
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u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
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u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
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icache_enable();
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
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/* Setup of core volatage selection pin to run at 1.4V */
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writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
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gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
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/* Setup of input daisy chains for SD card pins*/
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
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/* Setup of digital output for USB power and OC */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
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gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
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writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
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gpio_direction_input(IMX_GPIO_NR(1, 18));
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/* Setup of digital output control pins */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
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writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
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writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
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writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
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/* Switch both output drivers off */
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gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
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gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
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/* Setup of key input pin GPIO2[29]*/
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writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
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writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
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gpio_direction_input(IMX_GPIO_NR(2, 29));
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/* Setup of status LED outputs */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
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/* Switch both LEDs off */
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gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
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gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
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/* Setup of CAN1 and CAN2 signals */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
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/* Setup of input daisy chains for CAN signals*/
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writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
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writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
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/* Setup of I2C3 signals */
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writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
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writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
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/* Setup of input daisy chains for I2C3 signals*/
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writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
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writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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const char *e;
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#ifdef CONFIG_FEC_MXC
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struct iomuxc_mux_ctl *muxctl;
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u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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/*
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* fec pin init is generic
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*/
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mx25_fec_init_pins();
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/*
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* Set up LAN-RESET and FEC_RX_ERR
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*
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* LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
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* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
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*/
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
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writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
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/* assert PHY reset (low) */
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gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
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udelay(5000);
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/* deassert PHY reset */
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gpio_set_value(IMX_GPIO_NR(3, 16), 1);
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udelay(5000);
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#endif
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e = getenv("gs_base_board");
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if (e != NULL) {
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if (strcmp(e, "G283") == 0) {
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int key = gpio_get_value(IMX_GPIO_NR(2, 29));
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if (key) {
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/* Switch on both LEDs to inidcate boot mode */
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gpio_set_value(IMX_GPIO_NR(1, 29), 0);
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gpio_set_value(IMX_GPIO_NR(4, 21), 0);
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setenv("preboot", "run gs_slow_boot");
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} else
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setenv("preboot", "run gs_fast_boot");
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}
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}
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return 0;
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}
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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