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https://github.com/brain-hackers/u-boot-brain
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![Kumar Gala](/assets/img/avatar_default.png)
eg. because of rounding error we can get 799Mhz instead of 800Mhz. Introduced DIV_ROUND_UP and roundup taken from linux kernel. Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
277 lines
6.3 KiB
C
277 lines
6.3 KiB
C
/*
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cpu_type {
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char name[15];
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u32 soc_ver;
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};
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#define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
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struct cpu_type cpu_type_list [] = {
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CPU_TYPE_ENTRY(8533),
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CPU_TYPE_ENTRY(8533_E),
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CPU_TYPE_ENTRY(8540),
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CPU_TYPE_ENTRY(8541),
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CPU_TYPE_ENTRY(8541_E),
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CPU_TYPE_ENTRY(8543),
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CPU_TYPE_ENTRY(8543_E),
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CPU_TYPE_ENTRY(8544),
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CPU_TYPE_ENTRY(8544_E),
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CPU_TYPE_ENTRY(8545),
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CPU_TYPE_ENTRY(8545_E),
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CPU_TYPE_ENTRY(8547_E),
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CPU_TYPE_ENTRY(8548),
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CPU_TYPE_ENTRY(8548_E),
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CPU_TYPE_ENTRY(8555),
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CPU_TYPE_ENTRY(8555_E),
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CPU_TYPE_ENTRY(8560),
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CPU_TYPE_ENTRY(8567),
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CPU_TYPE_ENTRY(8567_E),
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CPU_TYPE_ENTRY(8568),
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CPU_TYPE_ENTRY(8568_E),
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CPU_TYPE_ENTRY(8572),
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CPU_TYPE_ENTRY(8572_E),
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};
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int checkcpu (void)
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{
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sys_info_t sysinfo;
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uint lcrr; /* local bus clock ratio register */
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uint clkdiv; /* clock divider portion of lcrr */
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uint pvr, svr;
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uint fam;
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uint ver;
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uint major, minor;
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int i;
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u32 ddr_ratio;
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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svr = get_svr();
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ver = SVR_SOC_VER(svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: ");
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for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
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if (cpu_type_list[i].soc_ver == ver) {
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puts(cpu_type_list[i].name);
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break;
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}
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if (i == ARRAY_SIZE(cpu_type_list))
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puts("Unknown");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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pvr = get_pvr();
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fam = PVR_FAM(pvr);
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ver = PVR_VER(pvr);
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major = PVR_MAJ(pvr);
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minor = PVR_MIN(pvr);
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printf("Core: ");
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switch (fam) {
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case PVR_FAM(PVR_85xx):
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puts("E500");
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break;
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default:
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puts("Unknown");
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break;
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}
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
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get_sys_info(&sysinfo);
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puts("Clock Configuration:\n");
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printf(" CPU:%4lu MHz, ", DIV_ROUND_UP(sysinfo.freqProcessor,1000000));
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printf("CCB:%4lu MHz,\n", DIV_ROUND_UP(sysinfo.freqSystemBus,1000000));
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ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
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switch (ddr_ratio) {
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case 0x0:
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printf(" DDR:%4lu MHz (%lu MT/s data rate), ",
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DIV_ROUND_UP(sysinfo.freqDDRBus,2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
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break;
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case 0x7:
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printf(" DDR:%4lu MHz (%lu MT/s data rate) (Synchronous), ",
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DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus, 1000000));
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break;
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default:
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printf(" DDR:%4lu MHz (%lu MT/s data rate) (Asynchronous), ",
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DIV_ROUND_UP(sysinfo.freqDDRBus, 2000000), DIV_ROUND_UP(sysinfo.freqDDRBus,1000000));
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break;
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}
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#if defined(CFG_LBC_LCRR)
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lcrr = CFG_LBC_LCRR;
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#else
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{
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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lcrr = lbc->lcrr;
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}
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#endif
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clkdiv = lcrr & 0x0f;
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if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
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#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
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/*
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider values.
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*/
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clkdiv *= 2;
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#endif
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printf("LBC:%4lu MHz\n",
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DIV_ROUND_UP(sysinfo.freqSystemBus, 1000000) / clkdiv);
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} else {
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printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
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}
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#ifdef CONFIG_CPM2
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printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
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#endif
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puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
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{
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uint pvr;
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uint ver;
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pvr = get_pvr();
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ver = PVR_VER(pvr);
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if (ver & 1){
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/* e500 v2 core has reset control register */
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volatile unsigned int * rstcr;
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rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
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*rstcr = 0x2; /* HRESET_REQ */
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}else{
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/*
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* Initiate hard reset in debug control register DBCR0
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* Make sure MSR[DE] = 1
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*/
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unsigned long val, msr;
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msr = mfmsr ();
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msr |= MSR_DE;
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mtmsr (msr);
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val = mfspr(DBCR0);
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val |= 0x70000000;
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mtspr(DBCR0,val);
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}
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return 1;
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}
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/*
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* Get timebase clock frequency
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*/
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unsigned long get_tbclk (void)
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{
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return (gd->bus_clk + 4UL)/8UL;
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}
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#if defined(CONFIG_WATCHDOG)
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void
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watchdog_reset(void)
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{
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int re_enable = disable_interrupts();
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reset_85xx_watchdog();
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if (re_enable) enable_interrupts();
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}
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void
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reset_85xx_watchdog(void)
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{
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/*
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* Clear TSR(WIS) bit by writing 1
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*/
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unsigned long val;
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val = mfspr(SPRN_TSR);
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val |= TSR_WIS;
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mtspr(SPRN_TSR, val);
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}
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_DDR_ECC)
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void dma_init(void) {
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volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
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dma->satr0 = 0x02c40000;
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dma->datr0 = 0x02c40000;
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dma->sr0 = 0xfffffff; /* clear any errors */
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asm("sync; isync; msync");
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return;
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}
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uint dma_check(void) {
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volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
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volatile uint status = dma->sr0;
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/* While the channel is busy, spin */
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while((status & 4) == 4) {
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status = dma->sr0;
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}
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/* clear MR0[CS] channel start bit */
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dma->mr0 &= 0x00000001;
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asm("sync;isync;msync");
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if (status != 0) {
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printf ("DMA Error: status = %x\n", status);
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}
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return status;
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}
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int dma_xfer(void *dest, uint count, void *src) {
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volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
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dma->dar0 = (uint) dest;
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dma->sar0 = (uint) src;
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dma->bcr0 = count;
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dma->mr0 = 0xf000004;
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asm("sync;isync;msync");
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dma->mr0 = 0xf000005;
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asm("sync;isync;msync");
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return dma_check();
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}
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#endif
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