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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-13 00:03:26 +09:00
![Marek Vasut](/assets/img/avatar_default.png)
In case the KS8851 has external EEPROM attached to it, do not set eth1addr at all. The network stack will read the MAC out of the KS8851 and set eth1addr accordingly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
742 lines
18 KiB
C
742 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <adc.h>
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#include <log.h>
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#include <net.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <bootm.h>
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#include <clk.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <env.h>
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#include <env_internal.h>
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#include <g_dnl.h>
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#include <generic-phy.h>
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#include <hang.h>
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#include <i2c.h>
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#include <i2c_eeprom.h>
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#include <init.h>
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#include <led.h>
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#include <memalign.h>
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#include <misc.h>
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#include <mtd.h>
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#include <mtd_node.h>
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#include <netdev.h>
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#include <phy.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#include <remoteproc.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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#include <watchdog.h>
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#include "../../st/common/stpmic1.h"
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/* SYSCFG registers */
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#define SYSCFG_BOOTR 0x00
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_IOCTRLSETR 0x18
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#define SYSCFG_ICNR 0x1C
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_PMCCLRR 0x44
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
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#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
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/*
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* Get a global data pointer
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*/
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DECLARE_GLOBAL_DATA_PTR;
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#define KS_CCR 0x08
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#define KS_CCR_EEPROM BIT(9)
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#define KS_BE0 BIT(12)
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#define KS_BE1 BIT(13)
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int setup_mac_address(void)
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{
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unsigned char enetaddr[6];
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bool skip_eth0 = false;
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bool skip_eth1 = false;
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struct udevice *dev;
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int off, ret;
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ret = eth_env_get_enetaddr("ethaddr", enetaddr);
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if (ret) /* ethaddr is already set */
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skip_eth0 = true;
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off = fdt_path_offset(gd->fdt_blob, "ethernet1");
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if (off < 0) {
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/* ethernet1 is not present in the system */
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skip_eth1 = true;
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goto out_set_ethaddr;
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}
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ret = eth_env_get_enetaddr("eth1addr", enetaddr);
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if (ret) {
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/* eth1addr is already set */
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skip_eth1 = true;
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goto out_set_ethaddr;
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}
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ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll");
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if (ret)
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goto out_set_ethaddr;
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/*
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* KS8851 with EEPROM may use custom MAC from EEPROM, read
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* out the KS8851 CCR register to determine whether EEPROM
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* is present. If EEPROM is present, it must contain valid
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* MAC address.
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*/
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u32 reg, ccr;
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reg = fdt_get_base_address(gd->fdt_blob, off);
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if (!reg)
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goto out_set_ethaddr;
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writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
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ccr = readw(reg);
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if (ccr & KS_CCR_EEPROM) {
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skip_eth1 = true;
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goto out_set_ethaddr;
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}
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out_set_ethaddr:
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if (skip_eth0 && skip_eth1)
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return 0;
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off = fdt_path_offset(gd->fdt_blob, "eeprom0");
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if (off < 0) {
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printf("%s: No eeprom0 path offset\n", __func__);
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return off;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
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if (ret) {
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printf("Cannot find EEPROM!\n");
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return ret;
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}
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ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
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if (ret) {
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printf("Error reading configuration EEPROM!\n");
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return ret;
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}
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if (is_valid_ethaddr(enetaddr)) {
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if (!skip_eth0)
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eth_env_set_enetaddr("ethaddr", enetaddr);
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enetaddr[5]++;
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if (!skip_eth1)
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eth_env_set_enetaddr("eth1addr", enetaddr);
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}
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return 0;
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}
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int checkboard(void)
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{
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char *mode;
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const char *fdt_compat;
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int fdt_compat_len;
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if (IS_ENABLED(CONFIG_TFABOOT))
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mode = "trusted";
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else
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mode = "basic";
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printf("Board: stm32mp1 in %s mode", mode);
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fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (fdt_compat && fdt_compat_len)
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printf(" (%s)", fdt_compat);
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puts("\n");
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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static u8 brdcode __section("data");
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static u8 ddr3code __section("data");
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static u8 somcode __section("data");
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static u32 opp_voltage_mv __section(".data");
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static void board_get_coding_straps(void)
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{
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struct gpio_desc gpio[4];
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ofnode node;
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int i, ret;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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printf("%s: no /config node?\n", __func__);
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return;
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}
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brdcode = 0;
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ddr3code = 0;
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somcode = 0;
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ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
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gpio, ARRAY_SIZE(gpio),
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GPIOD_IS_IN);
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for (i = 0; i < ret; i++)
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somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
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ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
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gpio, ARRAY_SIZE(gpio),
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GPIOD_IS_IN);
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for (i = 0; i < ret; i++)
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ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
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ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
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gpio, ARRAY_SIZE(gpio),
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GPIOD_IS_IN);
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for (i = 0; i < ret; i++)
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brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
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printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
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somcode, ddr3code, brdcode);
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}
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int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
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const char *name)
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{
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if (ddr3code == 1 &&
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!strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
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return 0;
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if (ddr3code == 2 &&
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!strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
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return 0;
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if (ddr3code == 3 &&
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!strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
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return 0;
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return -EINVAL;
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}
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void board_vddcore_init(u32 voltage_mv)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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opp_voltage_mv = voltage_mv;
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}
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int board_early_init_f(void)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD))
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stpmic1_init(opp_voltage_mv);
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board_get_coding_straps();
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return 0;
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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const char *compat;
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char test[128];
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compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
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snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d",
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compat, somcode, brdcode);
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if (!strcmp(name, test))
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return 0;
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return -EINVAL;
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}
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#endif
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#endif
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static void board_key_check(void)
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{
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#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
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ofnode node;
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struct gpio_desc gpio;
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enum forced_boot_mode boot_mode = BOOT_NORMAL;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return;
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}
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#ifdef CONFIG_FASTBOOT
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if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,fastboot-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("Fastboot key pressed, ");
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boot_mode = BOOT_FASTBOOT;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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#ifdef CONFIG_CMD_STM32PROG
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if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,stm32prog-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("STM32Programmer key pressed, ");
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boot_mode = BOOT_STM32PROG;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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if (boot_mode != BOOT_NORMAL) {
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puts("entering download mode...\n");
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_FORCED_MASK,
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boot_mode);
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}
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#endif
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}
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb/dwc2_udc.h>
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int g_dnl_board_usb_cable_connected(void)
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{
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struct udevice *dwc2_udc_otg;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
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DM_GET_DRIVER(dwc2_udc_otg),
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&dwc2_udc_otg);
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if (!ret)
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debug("dwc2_udc_otg init failed\n");
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return dwc2_udc_B_session_valid(dwc2_udc_otg);
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}
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#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
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#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
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int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
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{
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if (!strcmp(name, "usb_dnl_dfu"))
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put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
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else if (!strcmp(name, "usb_dnl_fastboot"))
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put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
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&dev->idProduct);
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else
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put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
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return 0;
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}
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#endif /* CONFIG_USB_GADGET */
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#ifdef CONFIG_LED
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static int get_led(struct udevice **dev, char *led_string)
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{
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
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if (!led_name) {
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pr_debug("%s: could not find %s config string\n",
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__func__, led_string);
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return -ENOENT;
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}
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ret = led_get_by_label(led_name, dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int setup_led(enum led_state_t cmd)
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{
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struct udevice *dev;
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int ret;
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ret = get_led(&dev, "u-boot,boot-led");
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if (ret)
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return ret;
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ret = led_set_state(dev, cmd);
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return ret;
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}
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#endif
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static void __maybe_unused led_error_blink(u32 nb_blink)
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{
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#ifdef CONFIG_LED
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int ret;
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struct udevice *led;
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u32 i;
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#endif
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if (!nb_blink)
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return;
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#ifdef CONFIG_LED
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ret = get_led(&led, "u-boot,error-led");
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if (!ret) {
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/* make u-boot,error-led blinking */
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/* if U32_MAX and 125ms interval, for 17.02 years */
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for (i = 0; i < 2 * nb_blink; i++) {
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led_set_state(led, LEDST_TOGGLE);
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mdelay(125);
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WATCHDOG_RESET();
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}
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}
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#endif
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/* infinite: the boot process must be stopped */
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if (nb_blink == U32_MAX)
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hang();
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}
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static void sysconf_init(void)
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{
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#ifndef CONFIG_TFABOOT
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u8 *syscfg;
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *pwr_dev;
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struct udevice *pwr_reg;
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struct udevice *dev;
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int ret;
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u32 otp = 0;
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#endif
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u32 bootr;
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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/* interconnect update : select master using the port 1 */
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/* LTDC = AXI_M9 */
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/* GPU = AXI_M8 */
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/* today information is hardcoded in U-Boot */
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writel(BIT(9), syscfg + SYSCFG_ICNR);
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/* disable Pull-Down for boot pin connected to VDD */
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bootr = readl(syscfg + SYSCFG_BOOTR);
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bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
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bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
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writel(bootr, syscfg + SYSCFG_BOOTR);
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#ifdef CONFIG_DM_REGULATOR
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/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* The customer will have to disable this for low frequencies
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* or if AFMUX is selected but the function not used, typically for
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* TRACE. Otherwise, impact on power consumption.
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*
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* WARNING:
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* enabling High Speed mode while VDD>2.7V
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* with the OTP product_below_2v5 (OTP 18, BIT 13)
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* erroneously set to 1 can damage the IC!
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* => U-Boot set the register only if VDD < 2.7V (in DT)
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* but this value need to be consistent with board design
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*/
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_GET_DRIVER(stm32mp_pwr_pmic),
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&pwr_dev);
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if (!ret) {
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (ret) {
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pr_err("Can't find stm32mp_bsec driver\n");
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return;
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}
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|
|
ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
|
|
if (ret > 0)
|
|
otp = otp & BIT(13);
|
|
|
|
/* get VDD = vdd-supply */
|
|
ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
|
|
&pwr_reg);
|
|
|
|
/* check if VDD is Low Voltage */
|
|
if (!ret) {
|
|
if (regulator_get_value(pwr_reg) < 2700000) {
|
|
writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_SPI,
|
|
syscfg + SYSCFG_IOCTRLSETR);
|
|
|
|
if (!otp)
|
|
pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
|
|
} else {
|
|
if (otp)
|
|
pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
|
|
}
|
|
} else {
|
|
debug("VDD unknown");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* activate automatic I/O compensation
|
|
* warning: need to ensure CSI enabled and ready in clock driver
|
|
*/
|
|
writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
|
|
|
|
while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
|
|
;
|
|
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
|
#endif
|
|
}
|
|
|
|
static void board_init_fmc2(void)
|
|
{
|
|
#define STM32_FMC2_BCR1 0x0
|
|
#define STM32_FMC2_BTR1 0x4
|
|
#define STM32_FMC2_BWTR1 0x104
|
|
#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
|
|
#define STM32_FMC2_BCRx_FMCEN BIT(31)
|
|
#define STM32_FMC2_BCRx_WREN BIT(12)
|
|
#define STM32_FMC2_BCRx_RSVD BIT(7)
|
|
#define STM32_FMC2_BCRx_FACCEN BIT(6)
|
|
#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
|
|
#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
|
|
#define STM32_FMC2_BCRx_MUXEN BIT(1)
|
|
#define STM32_FMC2_BCRx_MBKEN BIT(0)
|
|
#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
|
|
#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
|
|
#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
|
|
#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
|
|
#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
|
|
#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
|
|
|
|
#define RCC_MP_AHB6RSTCLRR 0x218
|
|
#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
|
|
#define RCC_MP_AHB6ENSETR 0x19c
|
|
#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
|
|
|
|
const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
|
|
STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
|
|
STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
|
|
STM32_FMC2_BCRx_MBKEN;
|
|
const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
|
|
STM32_FMC2_BTRx_BUSTURN(2) |
|
|
STM32_FMC2_BTRx_DATAST(0x22) |
|
|
STM32_FMC2_BTRx_ADDHLD(2) |
|
|
STM32_FMC2_BTRx_ADDSET(2);
|
|
|
|
/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
|
|
writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
|
|
writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
|
|
|
|
/* KS8851-16MLL -- Muxed mode */
|
|
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
|
|
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
|
|
/* AS7C34098 SRAM on X11 -- Muxed mode */
|
|
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
|
|
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
|
|
|
|
setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
|
|
}
|
|
|
|
/* board dependent setup after realloc */
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
|
|
|
|
if (CONFIG_IS_ENABLED(DM_GPIO_HOG))
|
|
gpio_hog_probe_all();
|
|
|
|
board_key_check();
|
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
regulators_enable_boot_on(_DEBUG);
|
|
#endif
|
|
|
|
sysconf_init();
|
|
|
|
board_init_fmc2();
|
|
|
|
if (CONFIG_IS_ENABLED(LED))
|
|
led_default_state();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
char *boot_device;
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
const void *fdt_compat;
|
|
int fdt_compat_len;
|
|
|
|
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
|
&fdt_compat_len);
|
|
if (fdt_compat && fdt_compat_len) {
|
|
if (strncmp(fdt_compat, "st,", 3) != 0)
|
|
env_set("board_name", fdt_compat);
|
|
else
|
|
env_set("board_name", fdt_compat + 3);
|
|
}
|
|
#endif
|
|
|
|
/* Check the boot-source to disable bootdelay */
|
|
boot_device = env_get("boot_device");
|
|
if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
|
|
env_set("bootdelay", "0");
|
|
|
|
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
|
env_set_ulong("dh_som_rev", somcode);
|
|
env_set_ulong("dh_board_rev", brdcode);
|
|
env_set_ulong("dh_ddr3_code", ddr3code);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
void board_quiesce_devices(void)
|
|
{
|
|
#ifdef CONFIG_LED
|
|
setup_led(LEDST_OFF);
|
|
#endif
|
|
}
|
|
|
|
/* eth init function : weak called in eqos driver */
|
|
int board_interface_eth_init(struct udevice *dev,
|
|
phy_interface_t interface_type)
|
|
{
|
|
u8 *syscfg;
|
|
u32 value;
|
|
bool eth_clk_sel_reg = false;
|
|
bool eth_ref_clk_sel_reg = false;
|
|
|
|
/* Gigabit Ethernet 125MHz clock selection. */
|
|
eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
|
|
|
|
/* Ethernet 50Mhz RMII clock selection */
|
|
eth_ref_clk_sel_reg =
|
|
dev_read_bool(dev, "st,eth_ref_clk_sel");
|
|
|
|
syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
|
|
|
|
if (!syscfg)
|
|
return -ENODEV;
|
|
|
|
switch (interface_type) {
|
|
case PHY_INTERFACE_MODE_MII:
|
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
|
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
|
|
debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
|
|
break;
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
if (eth_clk_sel_reg)
|
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
|
|
SYSCFG_PMCSETR_ETH_CLK_SEL;
|
|
else
|
|
value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
|
|
debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RMII:
|
|
if (eth_ref_clk_sel_reg)
|
|
value = SYSCFG_PMCSETR_ETH_SEL_RMII |
|
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
|
|
else
|
|
value = SYSCFG_PMCSETR_ETH_SEL_RMII;
|
|
debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
if (eth_clk_sel_reg)
|
|
value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
|
|
SYSCFG_PMCSETR_ETH_CLK_SEL;
|
|
else
|
|
value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
|
|
debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
|
|
break;
|
|
default:
|
|
debug("%s: Do not manage %d interface\n",
|
|
__func__, interface_type);
|
|
/* Do not manage others interfaces */
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* clear and set ETH configuration bits */
|
|
writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
|
|
SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
|
|
syscfg + SYSCFG_PMCCLRR);
|
|
writel(value, syscfg + SYSCFG_PMCSETR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void board_copro_image_process(ulong fw_image, size_t fw_size)
|
|
{
|
|
int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
|
|
|
|
if (!rproc_is_initialized())
|
|
if (rproc_init()) {
|
|
printf("Remote Processor %d initialization failed\n",
|
|
id);
|
|
return;
|
|
}
|
|
|
|
ret = rproc_load(id, fw_image, fw_size);
|
|
printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
|
|
id, fw_image, fw_size, ret ? " Failed!" : " Success!");
|
|
|
|
if (!ret) {
|
|
rproc_start(id);
|
|
env_set("copro_state", "booted");
|
|
}
|
|
}
|
|
|
|
U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
|