Prabhakar Kushwaha 6b50f62cc4 board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config ... The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>		2014-04-22 17:58:47 -07:00
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b4_pbi.cfg	board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config	2014-04-22 17:58:47 -07:00
b4_rcw.cfg	powerpc/b4860/pbl: fix rcw cfg	2014-01-02 14:10:14 -08:00
b4860qds_crossbar_con.h	board/b4860qds: Add support to make Aurora work on B4860QDS	2014-03-07 14:49:16 -08:00
b4860qds_qixis.h	SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode	2013-10-16 16:13:11 -07:00
b4860qds.c	powerpc/b4860: Add workaround for errata A006384 and A006475	2014-03-07 14:52:01 -08:00
b4860qds.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
ddr.c	Driver/DDR: Moving Freescale DDR driver to a common driver	2013-11-25 11:43:43 -08:00
eth_b4860qds.c	85xx/b4860: Alternate serdes protocols for B4860/B4420	2014-03-07 14:50:00 -08:00
law.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
Makefile	board: powerpc: convert makefiles to Kbuild style	2013-11-01 11:42:12 -04:00
pci.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
tlb.c	Coding Style cleanup: replace leading SPACEs by TABs	2013-10-14 16:06:54 -04:00