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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Alexey Brodkin](/assets/img/avatar_default.png)
Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
448 lines
11 KiB
C
448 lines
11 KiB
C
/*
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* (C) Copyright 2010
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Designware ethernet IP driver for u-boot
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <malloc.h>
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#include <linux/compiler.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include "designware.h"
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#if !defined(CONFIG_PHYLIB)
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# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
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#endif
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static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct eth_mac_regs *mac_p = bus->priv;
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ulong start;
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u16 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY))
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return readl(&mac_p->miidata);
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udelay(10);
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};
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return -1;
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}
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static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct eth_mac_regs *mac_p = bus->priv;
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ulong start;
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u16 miiaddr;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -1;
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}
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bus->read = dw_mdio_read;
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bus->write = dw_mdio_write;
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sprintf(bus->name, name);
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bus->priv = (void *)mac_regs_p;
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return mdio_register(bus);
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}
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static void tx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
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char *txbuffs = &priv->txbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
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DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
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DESC_TXSTS_TXCHECKINSCTRL | \
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DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
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desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
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desc_p->dmamac_cntl = 0;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
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#else
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desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
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desc_p->txrx_status = 0;
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#endif
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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/* Flush all Tx buffer descriptors at once */
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flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
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(unsigned int)priv->tx_mac_descrtable +
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sizeof(priv->tx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
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priv->tx_currdescnum = 0;
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}
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static void rx_descs_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
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char *rxbuffs = &priv->rxbuffs[0];
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struct dmamacdescr *desc_p;
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u32 idx;
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/* Before passing buffers to GMAC we need to make sure zeros
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* written there right after "priv" structure allocation were
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* flushed into RAM.
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* Otherwise there's a chance to get some of them flushed in RAM when
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* GMAC is already pushing data to RAM via DMA. This way incoming from
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* GMAC data will be corrupted. */
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flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
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RX_TOTAL_BUFSIZE);
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
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desc_p->dmamac_next = &desc_table_p[idx + 1];
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desc_p->dmamac_cntl =
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(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
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DESC_RXCTRL_RXCHAIN;
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desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
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}
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/* Correcting the last pointer of the chain */
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desc_p->dmamac_next = &desc_table_p[0];
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/* Flush all Rx buffer descriptors at once */
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flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
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(unsigned int)priv->rx_mac_descrtable +
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sizeof(priv->rx_mac_descrtable));
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writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
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priv->rx_currdescnum = 0;
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}
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static int dw_write_hwaddr(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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u32 macid_lo, macid_hi;
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u8 *mac_id = &dev->enetaddr[0];
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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writel(macid_lo, &mac_p->macaddr0lo);
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return 0;
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}
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static void dw_adjust_link(struct eth_mac_regs *mac_p,
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struct phy_device *phydev)
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{
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u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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if (phydev->speed != 1000)
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conf |= MII_PORTSELECT;
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if (phydev->speed == 100)
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conf |= FES_100;
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if (phydev->duplex)
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conf |= FULLDPLXMODE;
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writel(conf, &mac_p->conf);
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printf("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
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static void dw_eth_halt(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
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writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
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phy_shutdown(priv->phydev);
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}
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static int dw_eth_init(struct eth_device *dev, bd_t *bis)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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unsigned int start;
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writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
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start = get_timer(0);
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while (readl(&dma_p->busmode) & DMAMAC_SRST) {
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if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
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return -1;
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mdelay(100);
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};
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/* Soft reset above clears HW address registers.
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* So we have to set it here once again */
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dw_write_hwaddr(dev);
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rx_descs_init(dev);
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tx_descs_init(dev);
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
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writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
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&dma_p->opmode);
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writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
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/* Start up the PHY */
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if (phy_startup(priv->phydev)) {
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printf("Could not initialize PHY %s\n",
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priv->phydev->dev->name);
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return -1;
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}
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dw_adjust_link(mac_p, priv->phydev);
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if (!priv->phydev->link)
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return -1;
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writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
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return 0;
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}
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static int dw_eth_send(struct eth_device *dev, void *packet, int length)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 desc_num = priv->tx_currdescnum;
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struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
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/* Invalidate only "status" field for the following check */
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invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
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(unsigned long)&desc_p->txrx_status +
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sizeof(desc_p->txrx_status));
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/* Check if the descriptor is owned by CPU */
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if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
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printf("CPU not owner of tx frame\n");
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return -1;
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}
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memcpy((void *)desc_p->dmamac_addr, packet, length);
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/* Flush data to be sent */
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flush_dcache_range((unsigned long)desc_p->dmamac_addr,
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(unsigned long)desc_p->dmamac_addr + length);
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#if defined(CONFIG_DW_ALTDESCRIPTOR)
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desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
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desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK;
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desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
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desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
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#else
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desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
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DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
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DESC_TXCTRL_TXFIRST;
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desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
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#endif
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/* Flush modified buffer descriptor */
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flush_dcache_range((unsigned long)desc_p,
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(unsigned long)desc_p + sizeof(struct dmamacdescr));
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_TX_DESCR_NUM)
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desc_num = 0;
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priv->tx_currdescnum = desc_num;
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/* Start the transmission */
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writel(POLL_DATA, &dma_p->txpolldemand);
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return 0;
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}
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static int dw_eth_recv(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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u32 status, desc_num = priv->rx_currdescnum;
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struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
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int length = 0;
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/* Invalidate entire buffer descriptor */
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invalidate_dcache_range((unsigned long)desc_p,
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(unsigned long)desc_p +
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sizeof(struct dmamacdescr));
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status = desc_p->txrx_status;
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/* Check if the owner is the CPU */
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if (!(status & DESC_RXSTS_OWNBYDMA)) {
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length = (status & DESC_RXSTS_FRMLENMSK) >> \
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DESC_RXSTS_FRMLENSHFT;
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/* Invalidate received data */
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invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
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(unsigned long)desc_p->dmamac_addr +
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length);
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NetReceive(desc_p->dmamac_addr, length);
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/*
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* Make the current descriptor valid again and go to
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* the next one
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*/
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desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
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/* Flush only status field - others weren't changed */
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flush_dcache_range((unsigned long)&desc_p->txrx_status,
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(unsigned long)&desc_p->txrx_status +
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sizeof(desc_p->txrx_status));
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/* Test the wrap-around condition. */
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if (++desc_num >= CONFIG_RX_DESCR_NUM)
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desc_num = 0;
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}
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priv->rx_currdescnum = desc_num;
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return length;
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}
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static int dw_phy_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct phy_device *phydev;
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int mask = 0xffffffff;
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#ifdef CONFIG_PHY_ADDR
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mask = 1 << CONFIG_PHY_ADDR;
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#endif
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phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
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if (!phydev)
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return -1;
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phydev->supported &= PHY_GBIT_FEATURES;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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phy_config(phydev);
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return 1;
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}
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int designware_initialize(ulong base_addr, u32 interface)
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{
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struct eth_device *dev;
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struct dw_eth_dev *priv;
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dev = (struct eth_device *) malloc(sizeof(struct eth_device));
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if (!dev)
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return -ENOMEM;
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/*
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* Since the priv structure contains the descriptors which need a strict
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* buswidth alignment, memalign is used to allocate memory
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*/
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priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
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if (!priv) {
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free(dev);
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return -ENOMEM;
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}
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memset(dev, 0, sizeof(struct eth_device));
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memset(priv, 0, sizeof(struct dw_eth_dev));
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sprintf(dev->name, "dwmac.%lx", base_addr);
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dev->iobase = (int)base_addr;
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dev->priv = priv;
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priv->dev = dev;
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priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
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priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
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DW_DMA_BASE_OFFSET);
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dev->init = dw_eth_init;
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dev->send = dw_eth_send;
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dev->recv = dw_eth_recv;
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dev->halt = dw_eth_halt;
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dev->write_hwaddr = dw_write_hwaddr;
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eth_register(dev);
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priv->interface = interface;
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dw_mdio_init(dev->name, priv->mac_regs_p);
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priv->bus = miiphy_get_dev_by_name(dev->name);
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return dw_phy_init(dev);
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}
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