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https://github.com/brain-hackers/u-boot-brain
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52f7d8442e
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: Tom Rini <trini@ti.com>
36 lines
807 B
C
36 lines
807 B
C
/*
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* clocks_am33xx.h
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*
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* AM33xx clock define
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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/* MAIN PLL Fdll supported frequencies */
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#define MPUPLL_M_1000 1000
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#define MPUPLL_M_800 800
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#define MPUPLL_M_720 720
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#define MPUPLL_M_600 600
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#define MPUPLL_M_550 550
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#define MPUPLL_M_300 300
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/* MAIN PLL Fdll = 550 MHz, by default */
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#ifndef CONFIG_SYS_MPUCLK
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#define CONFIG_SYS_MPUCLK MPUPLL_M_550
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#endif
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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extern void enable_dmm_clocks(void);
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extern const struct dpll_params dpll_core_opp100;
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extern struct dpll_params dpll_mpu_opp100;
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#endif /* endif _CLOCKS_AM33XX_H_ */
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