mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-06 04:43:21 +09:00
52c411805c
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
251 lines
6.7 KiB
C
251 lines
6.7 KiB
C
/*
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* (C) Copyright 2008-2009
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* Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
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*
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* (C) Copyright 2009
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* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2004
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* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* (C) Copyright 2003-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#if defined(CONFIG_DDR_MT46V16M16)
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#include "mt46v16m16-75.h"
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#elif defined(CONFIG_SDR_MT48LC16M16A2)
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#include "mt48lc16m16a2-75.h"
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#elif defined(CONFIG_DDR_MT46V32M16)
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#include "mt46v32m16.h"
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#elif defined(CONFIG_DDR_HYB25D512160BF)
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#include "hyb25d512160bf.h"
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#elif defined(CONFIG_DDR_K4H511638C)
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#include "k4h511638c.h"
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#else
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#error "INKA4x0 SDRAM: invalid chip type specified!"
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#endif
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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volatile struct mpc5xxx_sdram *sdram =
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(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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/* unlock mode register */
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out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
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/* precharge all banks */
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out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
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#if SDRAM_DDR
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/* set mode register: extended mode */
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out_be32(&sdram->mode, SDRAM_EMODE);
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/* set mode register: reset DLL */
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out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
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#endif
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/* precharge all banks */
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out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
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/* auto refresh */
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out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
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/* set mode register */
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out_be32(&sdram->mode, SDRAM_MODE);
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/* normal operation */
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out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram(void)
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{
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volatile struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
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volatile struct mpc5xxx_cdm *cdm =
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(struct mpc5xxx_cdm *) MPC5XXX_CDM;
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volatile struct mpc5xxx_sdram *sdram =
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(struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
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ulong dramsize = 0;
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#ifndef CONFIG_SYS_RAMBOOT
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long test1, test2;
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/* setup SDRAM chip selects */
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out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
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out_be32(&mm->sdram1, 0x40000000); /* disabled */
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/* setup config registers */
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out_be32(&sdram->config1, SDRAM_CONFIG1);
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out_be32(&sdram->config2, SDRAM_CONFIG2);
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#if SDRAM_DDR
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/* set tap delay */
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out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32(&mm->sdram0, 0x13 +
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__builtin_ffs(dramsize >> 20) - 1);
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} else {
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out_be32(&mm->sdram0, 0); /* disabled */
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}
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out_be32(&mm->sdram1, dramsize); /* disabled */
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32(&mm->sdram0) & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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#endif /* CONFIG_SYS_RAMBOOT */
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return dramsize;
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}
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int checkboard (void)
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{
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puts ("Board: INKA 4X0\n");
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return 0;
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}
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void flash_preinit(void)
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{
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volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
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/*
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* Now, when we are in RAM, enable flash write
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* access for detection process.
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* Note that CS_BOOT (CS0) cannot be cleared when
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* executing in flash.
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*/
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clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
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}
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int misc_init_f (void)
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{
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volatile struct mpc5xxx_gpio *gpio =
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(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
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volatile struct mpc5xxx_wu_gpio *wu_gpio =
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(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
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volatile struct mpc5xxx_gpt *gpt;
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char tmp[10];
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int i, br;
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i = getenv_f("brightness", tmp, sizeof(tmp));
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br = (i > 0)
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? (int) simple_strtoul (tmp, NULL, 10)
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: CONFIG_SYS_BRIGHTNESS;
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if (br > 255)
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br = 255;
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/* Initialize GPIO output pins.
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*/
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/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
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for (i = 0; i <= 5; i++) {
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gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
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out_be32(&gpt->emsr, 0x34);
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}
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/* Configure GPT7 as PWM timer, 1kHz, no ints. */
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gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
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out_be32(&gpt->emsr, 0); /* Disable */
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out_be32(&gpt->cir, 0x020000fe);
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out_be32(&gpt->pwmcr, (br << 16));
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out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
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/* Configure PSC3_6,7 as GPIO output */
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setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
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MPC5XXX_GPIO_SIMPLE_PSC3_7);
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setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
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MPC5XXX_GPIO_SIMPLE_PSC3_7);
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/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
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setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 |
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MPC5XXX_GPIO_WKUP_7 |
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MPC5XXX_GPIO_WKUP_PSC3_9);
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setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 |
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MPC5XXX_GPIO_WKUP_7 |
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MPC5XXX_GPIO_WKUP_PSC3_9);
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/* Set LR mirror bit because it is low-active */
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setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
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/* Reset Coral-P graphics controller */
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setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
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/* Enable display backlight */
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clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
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setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
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setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
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setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
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/*
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* Configure three wire serial interface to RTC (PSC1_4,
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* PSC2_4, PSC3_4, PSC3_5)
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*/
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setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
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MPC5XXX_GPIO_WKUP_PSC2_4);
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setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
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MPC5XXX_GPIO_WKUP_PSC2_4);
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clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
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clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
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MPC5XXX_GPIO_SINT_PSC3_5);
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setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
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MPC5XXX_GPIO_SINT_PSC3_5);
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setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
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clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
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return 0;
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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